| Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame^] | 1 | /** @file
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| 2 | Intel FSP Info Header definition from Intel Firmware Support Package External
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| 3 | Architecture Specification, April 2014, revision 001.
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| 4 |
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| 5 | Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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| 6 | This program and the accompanying materials
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| 7 | are licensed and made available under the terms and conditions of the BSD License
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| 8 | which accompanies this distribution. The full text of the license may be found at
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| 9 | http://opensource.org/licenses/bsd-license.php.
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| 10 |
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| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 13 |
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| 14 | **/
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| 15 |
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| 16 | #ifndef _FSP_INFO_HEADER_H_
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| 17 | #define _FSP_INFO_HEADER_H_
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| 18 |
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| 19 | #define FSP_HEADER_REVISION_1 1
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| 20 | #define FSP_HEADER_REVISION_2 2
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| 21 |
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| 22 | #define FSPE_HEADER_REVISION_1 1
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| 23 | #define FSPP_HEADER_REVISION_1 1
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| 24 |
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| 25 | ///
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| 26 | /// Fixed FSP header offset in the FSP image
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| 27 | ///
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| 28 | #define FSP_INFO_HEADER_OFF 0x94
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| 29 |
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| 30 | #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
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| 31 |
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| 32 | #pragma pack(1)
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| 33 |
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| 34 | typedef struct {
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| 35 | ///
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| 36 | /// Byte 0x00: Signature ('FSPH') for the FSP Information Header
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| 37 | ///
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| 38 | UINT32 Signature;
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| 39 | ///
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| 40 | /// Byte 0x04: Length of the FSP Information Header
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| 41 | ///
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| 42 | UINT32 HeaderLength;
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| 43 | ///
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| 44 | /// Byte 0x08: Reserved
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| 45 | ///
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| 46 | UINT8 Reserved1[3];
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| 47 | ///
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| 48 | /// Byte 0x0B: Revision of the FSP Information Header
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| 49 | ///
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| 50 | UINT8 HeaderRevision;
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| 51 | ///
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| 52 | /// Byte 0x0C: Revision of the FSP binary
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| 53 | ///
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| 54 | UINT32 ImageRevision;
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| 55 |
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| 56 |
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| 57 | ///
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| 58 | /// Byte 0x10: Signature string that will help match the FSP Binary to a supported
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| 59 | /// hardware configuration.
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| 60 | ///
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| 61 | CHAR8 ImageId[8];
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| 62 | ///
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| 63 | /// Byte 0x18: Size of the entire FSP binary
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| 64 | ///
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| 65 | UINT32 ImageSize;
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| 66 | ///
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| 67 | /// Byte 0x18: FSP binary preferred base address
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| 68 | ///
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| 69 | UINT32 ImageBase;
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| 70 |
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| 71 |
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| 72 | ///
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| 73 | /// Byte 0x20: Attribute for the FSP binary
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| 74 | ///
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| 75 | UINT32 ImageAttribute;
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| 76 | ///
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| 77 | /// Byte 0x24: Offset of the FSP configuration region
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| 78 | ///
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| 79 | UINT32 CfgRegionOffset;
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| 80 | ///
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| 81 | /// Byte 0x24: Size of the FSP configuration region
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| 82 | ///
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| 83 | UINT32 CfgRegionSize;
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| 84 | ///
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| 85 | /// Byte 0x2C: Number of API entries this FSP supports
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| 86 | ///
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| 87 | UINT32 ApiEntryNum;
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| 88 |
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| 89 |
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| 90 | ///
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| 91 | /// Byte 0x30: The offset for the API to setup a temporary stack till the memory
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| 92 | /// is initialized.
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| 93 | ///
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| 94 | UINT32 TempRamInitEntryOffset;
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| 95 | ///
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| 96 | /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)
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| 97 | ///
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| 98 | UINT32 FspInitEntryOffset;
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| 99 | ///
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| 100 | /// Byte 0x38: The offset for the API to inform the FSP about the different stages
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| 101 | /// in the boot process
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| 102 | ///
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| 103 | UINT32 NotifyPhaseEntryOffset;
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| 104 |
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| 105 | ///
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| 106 | /// Below field is added in FSP 1.1
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| 107 | ///
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| 108 |
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| 109 | ///
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| 110 | /// Byte 0x3C: The offset for the API to initialize the memory
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| 111 | ///
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| 112 | UINT32 FspMemoryInitEntryOffset;
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| 113 | ///
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| 114 | /// Byte 0x40: The offset for the API to tear down temporary RAM
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| 115 | ///
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| 116 | UINT32 TempRamExitEntryOffset;
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| 117 | ///
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| 118 | /// Byte 0x44: The offset for the API to initialize the CPU and chipset
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| 119 | ///
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| 120 | UINT32 FspSiliconInitEntryOffset;
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| 121 |
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| 122 | } FSP_INFO_HEADER;
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| 123 |
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| 124 | ///
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| 125 | /// Below structure is added in FSP 1.1
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| 126 | ///
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| 127 | typedef struct {
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| 128 | ///
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| 129 | /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header
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| 130 | ///
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| 131 | UINT32 Signature;
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| 132 | ///
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| 133 | /// Byte 0x04: Length of the FSP Extended Header
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| 134 | ///
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| 135 | UINT32 HeaderLength;
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| 136 | ///
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| 137 | /// Byte 0x08: Revision of the FSP Extended Header
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| 138 | ///
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| 139 | UINT8 Revision;
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| 140 | ///
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| 141 | /// Byte 0x09: Reserved for future use.
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| 142 | ///
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| 143 | UINT8 Reserved;
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| 144 | ///
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| 145 | /// Byte 0x0A: An OEM-supplied string that defines the OEM
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| 146 | ///
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| 147 | CHAR8 OemId[6];
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| 148 | ///
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| 149 | /// Byte 0x10: An OEM-supplied revision number. Larger numbers are assumed to be newer revisions.
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| 150 | ///
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| 151 | UINT32 OemRevision;
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| 152 |
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| 153 | } FSP_EXTENTED_HEADER;
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| 154 |
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| 155 | #pragma pack()
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| 156 |
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| 157 | #endif
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