tree 58b63a57f7d7a3c163d59dafa77262a097fc487e
parent d42bd3453af5dc81b6907be1b066b34ba0a0c979
author Minghuan Lian <Minghuan.Lian@freescale.com> 1426129129 +0800
committer York Sun <yorksun@freescale.com> 1429636759 -0700

pci/layerscape: fix link and class issues to support ls2085a

1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
   to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
   has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
   must set this bit before change DBI register value.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>