| commit | 14cfc4f3735d9704cb6a630ef302be596d380684 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Thu Mar 13 13:07:57 2014 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Tue May 13 09:13:59 2014 +0200 |
| tree | 23c759ab37c1368763488a5548813231cfa1d3d0 | |
| parent | 2df9d5c431fca07c9868a36b48ee771bde6b19e8 [diff] |
fpga: xilinx: Simplify load/dump/info function handling Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com>