tree 01d05a71d77785352afd7c0e006f26b1effa0c19
parent ada02b84636242f5142f74016dbedb50889e93d0
author Benoît Thébaudeau <benoit.thebaudeau@advansee.com> 1359544756 +0000
committer Stefano Babic <sbabic@denx.de> 1360673551 +0100

imx: mx6q DDR3 init: Fix RST_to_CKE

MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>