arch/arm/dts/sdm845.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * SDM845 SoC device tree source
 *
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		i2c9 = &i2c9;
		i2c10 = &i2c10;
		i2c11 = &i2c11;
		i2c12 = &i2c12;
		i2c13 = &i2c13;
		i2c14 = &i2c14;
		i2c15 = &i2c15;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
		spi5 = &spi5;
		spi6 = &spi6;
		spi7 = &spi7;
		spi8 = &spi8;
		spi9 = &spi9;
		spi10 = &spi10;
		spi11 = &spi11;
		spi12 = &spi12;
		spi13 = &spi13;
		spi14 = &spi14;
		spi15 = &spi15;
	};

	chosen { };

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};
	};

	cpus: cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x0>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <611>;
			dynamic-power-coefficient = <154>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
					cache-unified;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x100>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <611>;
			dynamic-power-coefficient = <154>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			next-level-cache = <&L2_100>;
			L2_100: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x200>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <611>;
			dynamic-power-coefficient = <154>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			next-level-cache = <&L2_200>;
			L2_200: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x300>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <611>;
			dynamic-power-coefficient = <154>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			#cooling-cells = <2>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			next-level-cache = <&L2_300>;
			L2_300: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x400>;
			clocks = <&cpufreq_hw 1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <442>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			operating-points-v2 = <&cpu4_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			next-level-cache = <&L2_400>;
			L2_400: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x500>;
			clocks = <&cpufreq_hw 1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <442>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			operating-points-v2 = <&cpu4_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			next-level-cache = <&L2_500>;
			L2_500: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x600>;
			clocks = <&cpufreq_hw 1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <442>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			operating-points-v2 = <&cpu4_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			next-level-cache = <&L2_600>;
			L2_600: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x700>;
			clocks = <&cpufreq_hw 1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <442>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			operating-points-v2 = <&cpu4_opp_table>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			next-level-cache = <&L2_700>;
			L2_700: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

				core6 {
					cpu = <&CPU6>;
				};

				core7 {
					cpu = <&CPU7>;
				};
			};
		};

		cpu_idle_states: idle-states {
			entry-method = "psci";

			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
				compatible = "arm,idle-state";
				idle-state-name = "little-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <350>;
				exit-latency-us = <461>;
				min-residency-us = <1890>;
				local-timer-stop;
			};

			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
				compatible = "arm,idle-state";
				idle-state-name = "big-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <264>;
				exit-latency-us = <621>;
				min-residency-us = <952>;
				local-timer-stop;
			};
		};

		domain-idle-states {
			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x4100c244>;
				entry-latency-us = <3263>;
				exit-latency-us = <6562>;
				min-residency-us = <9987>;
			};
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-sdm845", "qcom,scm";
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0 0x80000000 0 0>;
	};

	cpu0_opp_table: opp-table-cpu0 {
		compatible = "operating-points-v2";
		opp-shared;

		cpu0_opp1: opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-peak-kBps = <800000 4800000>;
		};

		cpu0_opp2: opp-403200000 {
			opp-hz = /bits/ 64 <403200000>;
			opp-peak-kBps = <800000 4800000>;
		};

		cpu0_opp3: opp-480000000 {
			opp-hz = /bits/ 64 <480000000>;
			opp-peak-kBps = <800000 6451200>;
		};

		cpu0_opp4: opp-576000000 {
			opp-hz = /bits/ 64 <576000000>;
			opp-peak-kBps = <800000 6451200>;
		};

		cpu0_opp5: opp-652800000 {
			opp-hz = /bits/ 64 <652800000>;
			opp-peak-kBps = <800000 7680000>;
		};

		cpu0_opp6: opp-748800000 {
			opp-hz = /bits/ 64 <748800000>;
			opp-peak-kBps = <1804000 9216000>;
		};

		cpu0_opp7: opp-825600000 {
			opp-hz = /bits/ 64 <825600000>;
			opp-peak-kBps = <1804000 9216000>;
		};

		cpu0_opp8: opp-902400000 {
			opp-hz = /bits/ 64 <902400000>;
			opp-peak-kBps = <1804000 10444800>;
		};

		cpu0_opp9: opp-979200000 {
			opp-hz = /bits/ 64 <979200000>;
			opp-peak-kBps = <1804000 11980800>;
		};

		cpu0_opp10: opp-1056000000 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-peak-kBps = <1804000 11980800>;
		};

		cpu0_opp11: opp-1132800000 {
			opp-hz = /bits/ 64 <1132800000>;
			opp-peak-kBps = <2188000 13516800>;
		};

		cpu0_opp12: opp-1228800000 {
			opp-hz = /bits/ 64 <1228800000>;
			opp-peak-kBps = <2188000 15052800>;
		};

		cpu0_opp13: opp-1324800000 {
			opp-hz = /bits/ 64 <1324800000>;
			opp-peak-kBps = <2188000 16588800>;
		};

		cpu0_opp14: opp-1420800000 {
			opp-hz = /bits/ 64 <1420800000>;
			opp-peak-kBps = <3072000 18124800>;
		};

		cpu0_opp15: opp-1516800000 {
			opp-hz = /bits/ 64 <1516800000>;
			opp-peak-kBps = <3072000 19353600>;
		};

		cpu0_opp16: opp-1612800000 {
			opp-hz = /bits/ 64 <1612800000>;
			opp-peak-kBps = <4068000 19353600>;
		};

		cpu0_opp17: opp-1689600000 {
			opp-hz = /bits/ 64 <1689600000>;
			opp-peak-kBps = <4068000 20889600>;
		};

		cpu0_opp18: opp-1766400000 {
			opp-hz = /bits/ 64 <1766400000>;
			opp-peak-kBps = <4068000 22425600>;
		};
	};

	cpu4_opp_table: opp-table-cpu4 {
		compatible = "operating-points-v2";
		opp-shared;

		cpu4_opp1: opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-peak-kBps = <800000 4800000>;
		};

		cpu4_opp2: opp-403200000 {
			opp-hz = /bits/ 64 <403200000>;
			opp-peak-kBps = <800000 4800000>;
		};

		cpu4_opp3: opp-480000000 {
			opp-hz = /bits/ 64 <480000000>;
			opp-peak-kBps = <1804000 4800000>;
		};

		cpu4_opp4: opp-576000000 {
			opp-hz = /bits/ 64 <576000000>;
			opp-peak-kBps = <1804000 4800000>;
		};

		cpu4_opp5: opp-652800000 {
			opp-hz = /bits/ 64 <652800000>;
			opp-peak-kBps = <1804000 4800000>;
		};

		cpu4_opp6: opp-748800000 {
			opp-hz = /bits/ 64 <748800000>;
			opp-peak-kBps = <1804000 4800000>;
		};

		cpu4_opp7: opp-825600000 {
			opp-hz = /bits/ 64 <825600000>;
			opp-peak-kBps = <2188000 9216000>;
		};

		cpu4_opp8: opp-902400000 {
			opp-hz = /bits/ 64 <902400000>;
			opp-peak-kBps = <2188000 9216000>;
		};

		cpu4_opp9: opp-979200000 {
			opp-hz = /bits/ 64 <979200000>;
			opp-peak-kBps = <2188000 9216000>;
		};

		cpu4_opp10: opp-1056000000 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-peak-kBps = <3072000 9216000>;
		};

		cpu4_opp11: opp-1132800000 {
			opp-hz = /bits/ 64 <1132800000>;
			opp-peak-kBps = <3072000 11980800>;
		};

		cpu4_opp12: opp-1209600000 {
			opp-hz = /bits/ 64 <1209600000>;
			opp-peak-kBps = <4068000 11980800>;
		};

		cpu4_opp13: opp-1286400000 {
			opp-hz = /bits/ 64 <1286400000>;
			opp-peak-kBps = <4068000 11980800>;
		};

		cpu4_opp14: opp-1363200000 {
			opp-hz = /bits/ 64 <1363200000>;
			opp-peak-kBps = <4068000 15052800>;
		};

		cpu4_opp15: opp-1459200000 {
			opp-hz = /bits/ 64 <1459200000>;
			opp-peak-kBps = <4068000 15052800>;
		};

		cpu4_opp16: opp-1536000000 {
			opp-hz = /bits/ 64 <1536000000>;
			opp-peak-kBps = <5412000 15052800>;
		};

		cpu4_opp17: opp-1612800000 {
			opp-hz = /bits/ 64 <1612800000>;
			opp-peak-kBps = <5412000 15052800>;
		};

		cpu4_opp18: opp-1689600000 {
			opp-hz = /bits/ 64 <1689600000>;
			opp-peak-kBps = <5412000 19353600>;
		};

		cpu4_opp19: opp-1766400000 {
			opp-hz = /bits/ 64 <1766400000>;
			opp-peak-kBps = <6220000 19353600>;
		};

		cpu4_opp20: opp-1843200000 {
			opp-hz = /bits/ 64 <1843200000>;
			opp-peak-kBps = <6220000 19353600>;
		};

		cpu4_opp21: opp-1920000000 {
			opp-hz = /bits/ 64 <1920000000>;
			opp-peak-kBps = <7216000 19353600>;
		};

		cpu4_opp22: opp-1996800000 {
			opp-hz = /bits/ 64 <1996800000>;
			opp-peak-kBps = <7216000 20889600>;
		};

		cpu4_opp23: opp-2092800000 {
			opp-hz = /bits/ 64 <2092800000>;
			opp-peak-kBps = <7216000 20889600>;
		};

		cpu4_opp24: opp-2169600000 {
			opp-hz = /bits/ 64 <2169600000>;
			opp-peak-kBps = <7216000 20889600>;
		};

		cpu4_opp25: opp-2246400000 {
			opp-hz = /bits/ 64 <2246400000>;
			opp-peak-kBps = <7216000 20889600>;
		};

		cpu4_opp26: opp-2323200000 {
			opp-hz = /bits/ 64 <2323200000>;
			opp-peak-kBps = <7216000 20889600>;
		};

		cpu4_opp27: opp-2400000000 {
			opp-hz = /bits/ 64 <2400000000>;
			opp-peak-kBps = <7216000 22425600>;
		};

		cpu4_opp28: opp-2476800000 {
			opp-hz = /bits/ 64 <2476800000>;
			opp-peak-kBps = <7216000 22425600>;
		};

		cpu4_opp29: opp-2553600000 {
			opp-hz = /bits/ 64 <2553600000>;
			opp-peak-kBps = <7216000 22425600>;
		};

		cpu4_opp30: opp-2649600000 {
			opp-hz = /bits/ 64 <2649600000>;
			opp-peak-kBps = <7216000 22425600>;
		};

		cpu4_opp31: opp-2745600000 {
			opp-hz = /bits/ 64 <2745600000>;
			opp-peak-kBps = <7216000 25497600>;
		};

		cpu4_opp32: opp-2803200000 {
			opp-hz = /bits/ 64 <2803200000>;
			opp-peak-kBps = <7216000 25497600>;
		};
	};

	dsi_opp_table: opp-table-dsi {
		compatible = "operating-points-v2";

		opp-19200000 {
			opp-hz = /bits/ 64 <19200000>;
			required-opps = <&rpmhpd_opp_min_svs>;
		};

		opp-180000000 {
			opp-hz = /bits/ 64 <180000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};

		opp-328580000 {
			opp-hz = /bits/ 64 <328580000>;
			required-opps = <&rpmhpd_opp_svs_l1>;
		};

		opp-358000000 {
			opp-hz = /bits/ 64 <358000000>;
			required-opps = <&rpmhpd_opp_nom>;
		};
	};

	qspi_opp_table: opp-table-qspi {
		compatible = "operating-points-v2";

		opp-19200000 {
			opp-hz = /bits/ 64 <19200000>;
			required-opps = <&rpmhpd_opp_min_svs>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};

		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			required-opps = <&rpmhpd_opp_nom>;
		};
	};

	qup_opp_table: opp-table-qup {
		compatible = "operating-points-v2";

		opp-50000000 {
			opp-hz = /bits/ 64 <50000000>;
			required-opps = <&rpmhpd_opp_min_svs>;
		};

		opp-75000000 {
			opp-hz = /bits/ 64 <75000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};

		opp-128000000 {
			opp-hz = /bits/ 64 <128000000>;
			required-opps = <&rpmhpd_opp_nom>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci: psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: power-domain-cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD1: power-domain-cpu1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD2: power-domain-cpu2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD3: power-domain-cpu3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD4: power-domain-cpu4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD5: power-domain-cpu5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD6: power-domain-cpu6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD7: power-domain-cpu7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CLUSTER_PD: power-domain-cluster {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_SLEEP_0>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: hyp-mem@85700000 {
			reg = <0 0x85700000 0 0x600000>;
			no-map;
		};

		xbl_mem: xbl-mem@85e00000 {
			reg = <0 0x85e00000 0 0x100000>;
			no-map;
		};

		aop_mem: aop-mem@85fc0000 {
			reg = <0 0x85fc0000 0 0x20000>;
			no-map;
		};

		aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85fe0000 0 0x20000>;
			no-map;
		};

		smem@86000000 {
			compatible = "qcom,smem";
			reg = <0x0 0x86000000 0 0x200000>;
			no-map;
			hwlocks = <&tcsr_mutex 3>;
		};

		tz_mem: tz@86200000 {
			reg = <0 0x86200000 0 0x2d00000>;
			no-map;
		};

		rmtfs_mem: rmtfs@88f00000 {
			compatible = "qcom,rmtfs-mem";
			reg = <0 0x88f00000 0 0x200000>;
			no-map;

			qcom,client-id = <1>;
			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
		};

		qseecom_mem: qseecom@8ab00000 {
			reg = <0 0x8ab00000 0 0x1400000>;
			no-map;
		};

		camera_mem: camera-mem@8bf00000 {
			reg = <0 0x8bf00000 0 0x500000>;
			no-map;
		};

		ipa_fw_mem: ipa-fw@8c400000 {
			reg = <0 0x8c400000 0 0x10000>;
			no-map;
		};

		ipa_gsi_mem: ipa-gsi@8c410000 {
			reg = <0 0x8c410000 0 0x5000>;
			no-map;
		};

		gpu_mem: gpu@8c415000 {
			reg = <0 0x8c415000 0 0x2000>;
			no-map;
		};

		adsp_mem: adsp@8c500000 {
			reg = <0 0x8c500000 0 0x1a00000>;
			no-map;
		};

		wlan_msa_mem: wlan-msa@8df00000 {
			reg = <0 0x8df00000 0 0x100000>;
			no-map;
		};

		mpss_region: mpss@8e000000 {
			reg = <0 0x8e000000 0 0x7800000>;
			no-map;
		};

		venus_mem: venus@95800000 {
			reg = <0 0x95800000 0 0x500000>;
			no-map;
		};

		cdsp_mem: cdsp@95d00000 {
			reg = <0 0x95d00000 0 0x800000>;
			no-map;
		};

		mba_region: mba@96500000 {
			reg = <0 0x96500000 0 0x200000>;
			no-map;
		};

		slpi_mem: slpi@96700000 {
			reg = <0 0x96700000 0 0x1400000>;
			no-map;
		};

		spss_mem: spss@97b00000 {
			reg = <0 0x97b00000 0 0x100000>;
			no-map;
		};

		mdata_mem: mpss-metadata {
			alloc-ranges = <0 0xa0000000 0 0x20000000>;
			size = <0 0x4000>;
			no-map;
		};

		cont_splash_mem: framebuffer@9d400000 {
			reg = <0 0x9d400000 0 0x2400000>;
			no-map;
		};

		fastrpc_mem: fastrpc {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
			reusable;
		};
	};

	adsp_pas: remoteproc-adsp {
		compatible = "qcom,sdm845-adsp-pas";

		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "wdog", "fatal", "ready",
				  "handover", "stop-ack";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		memory-region = <&adsp_mem>;

		qcom,qmp = <&aoss_qmp>;

		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		status = "disabled";

		glink-edge {
			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
			label = "lpass";
			qcom,remote-pid = <2>;
			mboxes = <&apss_shared 8>;

			apr {
				compatible = "qcom,apr-v2";
				qcom,glink-channels = "apr_audio_svc";
				qcom,domain = <APR_DOMAIN_ADSP>;
				#address-cells = <1>;
				#size-cells = <0>;
				qcom,intents = <512 20>;

				service@3 {
					reg = <APR_SVC_ADSP_CORE>;
					compatible = "qcom,q6core";
					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
				};

				q6afe: service@4 {
					compatible = "qcom,q6afe";
					reg = <APR_SVC_AFE>;
					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
					q6afedai: dais {
						compatible = "qcom,q6afe-dais";
						#address-cells = <1>;
						#size-cells = <0>;
						#sound-dai-cells = <1>;
					};
				};

				q6asm: service@7 {
					compatible = "qcom,q6asm";
					reg = <APR_SVC_ASM>;
					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
					q6asmdai: dais {
						compatible = "qcom,q6asm-dais";
						#address-cells = <1>;
						#size-cells = <0>;
						#sound-dai-cells = <1>;
						iommus = <&apps_smmu 0x1821 0x0>;
					};
				};

				q6adm: service@8 {
					compatible = "qcom,q6adm";
					reg = <APR_SVC_ADM>;
					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
					q6routing: routing {
						compatible = "qcom,q6adm-routing";
						#sound-dai-cells = <0>;
					};
				};

				q6mvm: apr-service@9 {
					compatible = "qcom,q6mvm";
					reg = <APR_SVC_ADSP_MVM>;
					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
					status = "disabled";

					q6voicedai: dais {
						compatible = "qcom,q6voice-dais";
						#sound-dai-cells = <1>;
					};
				};

				q6cvs: apr-service@a {
					compatible = "qcom,q6cvs";
					reg = <APR_SVC_ADSP_CVS>;
					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
					status = "disabled";
				};

				q6cvp: apr-service@b {
					compatible = "qcom,q6cvp";
					reg = <APR_SVC_ADSP_CVP>;
					qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
					status = "disabled";
				};
			};

			fastrpc {
				compatible = "qcom,fastrpc";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				label = "adsp";
				qcom,non-secure-domain;
				#address-cells = <1>;
				#size-cells = <0>;

				compute-cb@3 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <3>;
					iommus = <&apps_smmu 0x1823 0x0>;
				};

				compute-cb@4 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <4>;
					iommus = <&apps_smmu 0x1824 0x0>;
				};
			};
		};
	};

	cdsp_pas: remoteproc-cdsp {
		compatible = "qcom,sdm845-cdsp-pas";

		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
				      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
				      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
				      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
				      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "wdog", "fatal", "ready",
				  "handover", "stop-ack";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		memory-region = <&cdsp_mem>;

		qcom,qmp = <&aoss_qmp>;

		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		status = "disabled";

		glink-edge {
			interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
			label = "turing";
			qcom,remote-pid = <5>;
			mboxes = <&apss_shared 4>;
			fastrpc {
				compatible = "qcom,fastrpc";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				label = "cdsp";
				qcom,non-secure-domain;
				#address-cells = <1>;
				#size-cells = <0>;

				compute-cb@1 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <1>;
					iommus = <&apps_smmu 0x1401 0x30>;
				};

				compute-cb@2 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <2>;
					iommus = <&apps_smmu 0x1402 0x30>;
				};

				compute-cb@3 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <3>;
					iommus = <&apps_smmu 0x1403 0x30>;
				};

				compute-cb@4 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <4>;
					iommus = <&apps_smmu 0x1404 0x30>;
				};

				compute-cb@5 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <5>;
					iommus = <&apps_smmu 0x1405 0x30>;
				};

				compute-cb@6 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <6>;
					iommus = <&apps_smmu 0x1406 0x30>;
				};

				compute-cb@7 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <7>;
					iommus = <&apps_smmu 0x1407 0x30>;
				};

				compute-cb@8 {
					compatible = "qcom,fastrpc-compute-cb";
					reg = <8>;
					iommus = <&apps_smmu 0x1408 0x30>;
				};
			};
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;

		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apss_shared 6>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-lpass {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apss_shared 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-mpss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apss_shared 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		ipa_smp2p_out: ipa-ap-to-modem {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		ipa_smp2p_in: ipa-modem-to-ap {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;
		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apss_shared 26>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;

		slpi_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		slpi_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x10 0>;
		dma-ranges = <0 0 0 0 0x10 0>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sdm845";
			reg = <0 0x00100000 0 0x1f0000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>,
				 <&pcie0_phy>,
				 <&pcie1_phy>;
			clock-names = "bi_tcxo",
				      "bi_tcxo_ao",
				      "sleep_clk",
				      "pcie_0_pipe_clk",
				      "pcie_1_pipe_clk";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			power-domains = <&rpmhpd SDM845_CX>;
		};

		qfprom@784000 {
			compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
			reg = <0 0x00784000 0 0x8ff>;
			#address-cells = <1>;
			#size-cells = <1>;

			qusb2p_hstx_trim: hstx-trim-primary@1eb {
				reg = <0x1eb 0x1>;
				bits = <1 4>;
			};

			qusb2s_hstx_trim: hstx-trim-secondary@1eb {
				reg = <0x1eb 0x2>;
				bits = <6 4>;
			};
		};

		rng: rng@793000 {
			compatible = "qcom,prng-ee";
			reg = <0 0x00793000 0 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		gpi_dma0: dma-controller@800000 {
			#dma-cells = <3>;
			compatible = "qcom,sdm845-gpi-dma";
			reg = <0 0x00800000 0 0x60000>;
			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <13>;
			dma-channel-mask = <0xfa>;
			iommus = <&apps_smmu 0x0016 0x0>;
			status = "disabled";
		};

		qupv3_id_0: geniqup@8c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0 0x008c0000 0 0x6000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			iommus = <&apps_smmu 0x3 0x0>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
			interconnect-names = "qup-core";
			status = "disabled";

			i2c0: i2c@880000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00880000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c0_default>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi0: spi@880000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00880000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi0_default>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart0: serial@880000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00880000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart0_default>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c1: i2c@884000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00884000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c1_default>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi1: spi@884000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00884000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi1_default>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart1: serial@884000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00884000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart1_default>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c2: i2c@888000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00888000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c2_default>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi2: spi@888000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00888000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi2_default>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart2: serial@888000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00888000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart2_default>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c3: i2c@88c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x0088c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c3_default>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi3: spi@88c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x0088c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi3_default>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart3: serial@88c000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x0088c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart3_default>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c4: i2c@890000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00890000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c4_default>;
				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi4: spi@890000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00890000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi4_default>;
				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart4: serial@890000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00890000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart4_default>;
				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c5: i2c@894000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00894000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c5_default>;
				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi5: spi@894000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00894000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi5_default>;
				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart5: serial@894000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00894000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart5_default>;
				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c6: i2c@898000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00898000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c6_default>;
				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
						<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi6: spi@898000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00898000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi6_default>;
				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart6: serial@898000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00898000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart6_default>;
				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c7: i2c@89c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x0089c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c7_default>;
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				status = "disabled";
			};

			spi7: spi@89c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x0089c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi7_default>;
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart7: serial@89c000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x0089c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart7_default>;
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};
		};

		gpi_dma1: dma-controller@a00000 {
			#dma-cells = <3>;
			compatible = "qcom,sdm845-gpi-dma";
			reg = <0 0x00a00000 0 0x60000>;
			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <13>;
			dma-channel-mask = <0xfa>;
			iommus = <&apps_smmu 0x06d6 0x0>;
			status = "disabled";
		};

		qupv3_id_1: geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0 0x00ac0000 0 0x6000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			iommus = <&apps_smmu 0x6c3 0x0>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
			interconnect-names = "qup-core";
			status = "disabled";

			i2c8: i2c@a80000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a80000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c8_default>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi8: spi@a80000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a80000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi8_default>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart8: serial@a80000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a80000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart8_default>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c9: i2c@a84000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a84000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c9_default>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi9: spi@a84000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a84000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi9_default>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart9: serial@a84000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0 0x00a84000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart9_default>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c10: i2c@a88000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a88000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c10_default>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi10: spi@a88000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a88000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi10_default>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart10: serial@a88000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a88000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart10_default>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c11: i2c@a8c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a8c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c11_default>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi11: spi@a8c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a8c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi11_default>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart11: serial@a8c000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a8c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart11_default>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c12: i2c@a90000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a90000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c12_default>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi12: spi@a90000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a90000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi12_default>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart12: serial@a90000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a90000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart12_default>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c13: i2c@a94000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a94000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c13_default>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi13: spi@a94000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a94000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi13_default>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart13: serial@a94000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a94000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart13_default>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c14: i2c@a98000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a98000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c14_default>;
				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi14: spi@a98000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a98000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi14_default>;
				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart14: serial@a98000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a98000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart14_default>;
				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c15: i2c@a9c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a9c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c15_default>;
				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				status = "disabled";
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
			};

			spi15: spi@a9c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a9c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi15_default>;
				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart15: serial@a9c000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a9c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart15_default>;
				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SDM845_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
						<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};
		};

		llcc: system-cache-controller@1100000 {
			compatible = "qcom,sdm845-llcc";
			reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
			      <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
			      <0 0x01300000 0 0x50000>;
			reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
				    "llcc3_base", "llcc_broadcast_base";
			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
		};

		dma@10a2000 {
			compatible = "qcom,sdm845-dcc", "qcom,dcc";
			reg = <0x0 0x010a2000 0x0 0x1000>,
			      <0x0 0x010ae000 0x0 0x2000>;
		};

		pmu@114a000 {
			compatible = "qcom,sdm845-llcc-bwmon";
			reg = <0 0x0114a000 0 0x1000>;
			interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
			interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;

			operating-points-v2 = <&llcc_bwmon_opp_table>;

			llcc_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				/*
				 * The interconnect path bandwidth taken from
				 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
				 * interconnect.  This also matches the
				 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
				 * bus width: 4 bytes) from msm-4.9 downstream
				 * kernel.
				 */
				opp-0 {
					opp-peak-kBps = <800000>;
				};
				opp-1 {
					opp-peak-kBps = <1804000>;
				};
				opp-2 {
					opp-peak-kBps = <3072000>;
				};
				opp-3 {
					opp-peak-kBps = <5412000>;
				};
				opp-4 {
					opp-peak-kBps = <7216000>;
				};
			};
		};

		pmu@1436400 {
			compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
			reg = <0 0x01436400 0 0x600>;
			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
			interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;

			cpu_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				/*
				 * The interconnect path bandwidth taken from
				 * cpu4_opp_table bandwidth for OSM L3
				 * interconnect.  This also matches the OSM L3
				 * from bandwidth table of qcom,cpu4-l3lat-mon
				 * (qcom,core-dev-table, bus width: 16 bytes)
				 * from msm-4.9 downstream kernel.
				 */
				opp-0 {
					opp-peak-kBps = <4800000>;
				};
				opp-1 {
					opp-peak-kBps = <9216000>;
				};
				opp-2 {
					opp-peak-kBps = <15052800>;
				};
				opp-3 {
					opp-peak-kBps = <20889600>;
				};
				opp-4 {
					opp-peak-kBps = <25497600>;
				};
			};
		};

		pcie0: pci@1c00000 {
			compatible = "qcom,pcie-sdm845";
			reg = <0 0x01c00000 0 0x2000>,
			      <0 0x60000000 0 0xf1d>,
			      <0 0x60000f20 0 0xa8>,
			      <0 0x60100000 0 0x100000>,
			      <0 0x01c07000 0 0x1000>;
			reg-names = "parf", "dbi", "elbi", "config", "mhi";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;

			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;

			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
				 <&gcc GCC_PCIE_0_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
			clock-names = "pipe",
				      "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "tbu";

			iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
				    <0x100 &apps_smmu 0x1c11 0x1>,
				    <0x200 &apps_smmu 0x1c12 0x1>,
				    <0x300 &apps_smmu 0x1c13 0x1>,
				    <0x400 &apps_smmu 0x1c14 0x1>,
				    <0x500 &apps_smmu 0x1c15 0x1>,
				    <0x600 &apps_smmu 0x1c16 0x1>,
				    <0x700 &apps_smmu 0x1c17 0x1>,
				    <0x800 &apps_smmu 0x1c18 0x1>,
				    <0x900 &apps_smmu 0x1c19 0x1>,
				    <0xa00 &apps_smmu 0x1c1a 0x1>,
				    <0xb00 &apps_smmu 0x1c1b 0x1>,
				    <0xc00 &apps_smmu 0x1c1c 0x1>,
				    <0xd00 &apps_smmu 0x1c1d 0x1>,
				    <0xe00 &apps_smmu 0x1c1e 0x1>,
				    <0xf00 &apps_smmu 0x1c1f 0x1>;

			resets = <&gcc GCC_PCIE_0_BCR>;
			reset-names = "pci";

			power-domains = <&gcc PCIE_0_GDSC>;

			phys = <&pcie0_phy>;
			phy-names = "pciephy";

			status = "disabled";
		};

		pcie0_phy: phy@1c06000 {
			compatible = "qcom,sdm845-qmp-pcie-phy";
			reg = <0 0x01c06000 0 0x1000>;
			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_CLKREF_CLK>,
				 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
				 <&gcc GCC_PCIE_0_PIPE_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "refgen",
				      "pipe";

			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;

			#phy-cells = <0>;

			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
			reset-names = "phy";

			assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
			assigned-clock-rates = <100000000>;

			status = "disabled";
		};

		pcie1: pci@1c08000 {
			compatible = "qcom,pcie-sdm845";
			reg = <0 0x01c08000 0 0x2000>,
			      <0 0x40000000 0 0xf1d>,
			      <0 0x40000f20 0 0xa8>,
			      <0 0x40100000 0 0x100000>,
			      <0 0x01c0c000 0 0x1000>;
			reg-names = "parf", "dbi", "elbi", "config", "mhi";
			device_type = "pci";
			linux,pci-domain = <1>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;

			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;

			interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
				 <&gcc GCC_PCIE_1_AUX_CLK>,
				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_PCIE_1_CLKREF_CLK>,
				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
			clock-names = "pipe",
				      "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "ref",
				      "tbu";

			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
			assigned-clock-rates = <19200000>;

			iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
				    <0x100 &apps_smmu 0x1c01 0x1>,
				    <0x200 &apps_smmu 0x1c02 0x1>,
				    <0x300 &apps_smmu 0x1c03 0x1>,
				    <0x400 &apps_smmu 0x1c04 0x1>,
				    <0x500 &apps_smmu 0x1c05 0x1>,
				    <0x600 &apps_smmu 0x1c06 0x1>,
				    <0x700 &apps_smmu 0x1c07 0x1>,
				    <0x800 &apps_smmu 0x1c08 0x1>,
				    <0x900 &apps_smmu 0x1c09 0x1>,
				    <0xa00 &apps_smmu 0x1c0a 0x1>,
				    <0xb00 &apps_smmu 0x1c0b 0x1>,
				    <0xc00 &apps_smmu 0x1c0c 0x1>,
				    <0xd00 &apps_smmu 0x1c0d 0x1>,
				    <0xe00 &apps_smmu 0x1c0e 0x1>,
				    <0xf00 &apps_smmu 0x1c0f 0x1>;

			resets = <&gcc GCC_PCIE_1_BCR>;
			reset-names = "pci";

			power-domains = <&gcc PCIE_1_GDSC>;

			phys = <&pcie1_phy>;
			phy-names = "pciephy";

			status = "disabled";
		};

		pcie1_phy: phy@1c0a000 {
			compatible = "qcom,sdm845-qhp-pcie-phy";
			reg = <0 0x01c0a000 0 0x2000>;
			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_1_CLKREF_CLK>,
				 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
				 <&gcc GCC_PCIE_1_PIPE_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "refgen",
				      "pipe";

			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;

			#phy-cells = <0>;

			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
			reset-names = "phy";

			assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
			assigned-clock-rates = <100000000>;

			status = "disabled";
		};

		mem_noc: interconnect@1380000 {
			compatible = "qcom,sdm845-mem-noc";
			reg = <0 0x01380000 0 0x27200>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		dc_noc: interconnect@14e0000 {
			compatible = "qcom,sdm845-dc-noc";
			reg = <0 0x014e0000 0 0x400>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		config_noc: interconnect@1500000 {
			compatible = "qcom,sdm845-config-noc";
			reg = <0 0x01500000 0 0x5080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system_noc: interconnect@1620000 {
			compatible = "qcom,sdm845-system-noc";
			reg = <0 0x01620000 0 0x18080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre1_noc: interconnect@16e0000 {
			compatible = "qcom,sdm845-aggre1-noc";
			reg = <0 0x016e0000 0 0x15080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre2_noc: interconnect@1700000 {
			compatible = "qcom,sdm845-aggre2-noc";
			reg = <0 0x01700000 0 0x1f300>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		mmss_noc: interconnect@1740000 {
			compatible = "qcom,sdm845-mmss-noc";
			reg = <0 0x01740000 0 0x1c100>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		ufs_mem_hc: ufshc@1d84000 {
			compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
				     "jedec,ufs-2.0";
			reg = <0 0x01d84000 0 0x2500>,
			      <0 0x01d90000 0 0x8000>;
			reg-names = "std", "ice";
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufs_mem_phy_lanes>;
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			power-domains = <&gcc UFS_PHY_GDSC>;
			#reset-cells = <1>;
			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "rst";

			iommus = <&apps_smmu 0x100 0xf>;

			clock-names =
				"core_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk",
				"rx_lane1_sync_clk",
				"ice_core_clk";
			clocks =
				<&gcc GCC_UFS_PHY_AXI_CLK>,
				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				<&gcc GCC_UFS_PHY_AHB_CLK>,
				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				<&rpmhcc RPMH_CXO_CLK>,
				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
				<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
			freq-table-hz =
				<50000000 200000000>,
				<0 0>,
				<0 0>,
				<37500000 150000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>,
				<75000000 300000000>;

			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
					<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
			interconnect-names = "ufs-ddr", "cpu-ufs";

			status = "disabled";
		};

		ufs_mem_phy: phy@1d87000 {
			compatible = "qcom,sdm845-qmp-ufs-phy";
			reg = <0 0x01d87000 0 0x18c>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			clock-names = "ref",
				      "ref_aux";
			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

			resets = <&ufs_mem_hc 0>;
			reset-names = "ufsphy";
			status = "disabled";

			ufs_mem_phy_lanes: phy@1d87400 {
				reg = <0 0x01d87400 0 0x108>,
				      <0 0x01d87600 0 0x1e0>,
				      <0 0x01d87c00 0 0x1dc>,
				      <0 0x01d87800 0 0x108>,
				      <0 0x01d87a00 0 0x1e0>;
				#phy-cells = <0>;
			};
		};

		cryptobam: dma-controller@1dc4000 {
			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
			reg = <0 0x01dc4000 0 0x24000>;
			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rpmhcc RPMH_CE_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			iommus = <&apps_smmu 0x704 0x1>,
				 <&apps_smmu 0x706 0x1>,
				 <&apps_smmu 0x714 0x1>,
				 <&apps_smmu 0x716 0x1>;
		};

		crypto: crypto@1dfa000 {
			compatible = "qcom,crypto-v5.4";
			reg = <0 0x01dfa000 0 0x6000>;
			clocks = <&gcc GCC_CE1_AHB_CLK>,
				 <&gcc GCC_CE1_AXI_CLK>,
				 <&rpmhcc RPMH_CE_CLK>;
			clock-names = "iface", "bus", "core";
			dmas = <&cryptobam 6>, <&cryptobam 7>;
			dma-names = "rx", "tx";
			iommus = <&apps_smmu 0x704 0x1>,
				 <&apps_smmu 0x706 0x1>,
				 <&apps_smmu 0x714 0x1>,
				 <&apps_smmu 0x716 0x1>;
		};

		ipa: ipa@1e40000 {
			compatible = "qcom,sdm845-ipa";

			iommus = <&apps_smmu 0x720 0x0>,
				 <&apps_smmu 0x722 0x0>;
			reg = <0 0x01e40000 0 0x7000>,
			      <0 0x01e47000 0 0x2000>,
			      <0 0x01e04000 0 0x2c000>;
			reg-names = "ipa-reg",
				    "ipa-shared",
				    "gsi";

			interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
					      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "ipa",
					  "gsi",
					  "ipa-clock-query",
					  "ipa-setup-ready";

			clocks = <&rpmhcc RPMH_IPA_CLK>;
			clock-names = "core";

			interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
					<&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
					<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
			interconnect-names = "memory",
					     "imem",
					     "config";

			qcom,smem-states = <&ipa_smp2p_out 0>,
					   <&ipa_smp2p_out 1>;
			qcom,smem-state-names = "ipa-clock-enabled-valid",
						"ipa-clock-enabled";

			status = "disabled";
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0 0x01f40000 0 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr_regs_1: syscon@1f60000 {
			compatible = "qcom,sdm845-tcsr", "syscon";
			reg = <0 0x01f60000 0 0x20000>;
		};

		tlmm: pinctrl@3400000 {
			compatible = "qcom,sdm845-pinctrl";
			reg = <0 0x03400000 0 0xc00000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&tlmm 0 0 151>;
			wakeup-parent = <&pdc_intc>;

			cci0_default: cci0-default-state {
				/* SDA, SCL */
				pins = "gpio17", "gpio18";
				function = "cci_i2c";

				bias-pull-up;
				drive-strength = <2>; /* 2 mA */
			};

			cci0_sleep: cci0-sleep-state {
				/* SDA, SCL */
				pins = "gpio17", "gpio18";
				function = "cci_i2c";

				drive-strength = <2>; /* 2 mA */
				bias-pull-down;
			};

			cci1_default: cci1-default-state {
				/* SDA, SCL */
				pins = "gpio19", "gpio20";
				function = "cci_i2c";

				bias-pull-up;
				drive-strength = <2>; /* 2 mA */
			};

			cci1_sleep: cci1-sleep-state {
				/* SDA, SCL */
				pins = "gpio19", "gpio20";
				function = "cci_i2c";

				drive-strength = <2>; /* 2 mA */
				bias-pull-down;
			};

			qspi_clk: qspi-clk-state {
				pins = "gpio95";
				function = "qspi_clk";
			};

			qspi_cs0: qspi-cs0-state {
				pins = "gpio90";
				function = "qspi_cs";
			};

			qspi_cs1: qspi-cs1-state {
				pins = "gpio89";
				function = "qspi_cs";
			};

			qspi_data0: qspi-data0-state {
				pins = "gpio91";
				function = "qspi_data";
			};