tree 1c50f258015afe229f719c2da88ec4e2f4944fbe
parent 5af741f1e98457de626f01302138de20c948fd46
author Hans de Goede <hdegoede@redhat.com> 1417982971 +0100
committer Hans de Goede <hdegoede@redhat.com> 1421243797 +0100

sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them

Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.

This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>