tree 807d8add7a8000ba4939bb68b1d1fcbfef8e490f
parent 14109c7a6aa9d9a30da85ad9e6bbd502ba125abc
author York Sun <yorksun@freescale.com> 1414435511 -0700
committer York Sun <yorksun@freescale.com> 1417795568 -0800

powerpc/t1040qds: Update DDR option

Enable interactive debugging by default. Remove DDR controller interleaving
because this SoC only has one controller. Use auto chip-select interleaving
to detect number of ranks.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Poonam Aggrwal <poonam.aggrwal@freescale.com>