tree 927d5d9f7d9908ef42dae037cfdd313d7b1f3f98
parent c03cd98d1a163666b4addcdd9a34fc0c77dfd0a5
author Svyatoslav Ryhel <clamor95@gmail.com> 1688396814 +0300
committer Svyatoslav Ryhel <clamor95@gmail.com> 1703013851 +0200

ARM: tegra: clock: support get and set rate for simple PLL

Simple PLL clocks like PLLD2 were omitted since they do not share common
4 register structure with main clocks. Such clocks are containd in simple
PLL group. Only clock_start_pll function supported them. This patch expands
this support on clock_set_rate and clock_get_rate which should make
simple PLL clocks equal to main PLL clocks.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>