// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright (C) 2015, Freescale Semiconductor
 * Copyright 2020 NXP
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 */

/dts-v1/;
/include/ "fsl-ls1043a.dtsi"

/ {
	model = "LS1043A RDB Board";

        aliases {
		spi1 = &dspi0;
        };

};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	dspiflash: n25q12a {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <1000000>; /* input clock */
	};

};

&i2c0 {
	status = "okay";
	ina220@40 {
		compatible = "ti,ina220";
		reg = <0x40>;
		shunt-resistor = <1000>;
	};
	adt7461a@4c {
		compatible = "adi,adt7461a";
		reg = <0x4c>;
	};
	eeprom@52 {
		compatible = "at24,24c512";
		reg = <0x52>;
	};

	eeprom@53 {
		compatible = "at24,24c512";
		reg = <0x53>;
	};

	rtc@68 {
		compatible = "pericom,pt7c4338";
		reg = <0x68>;
	};
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, NAND Flashes and FPGA on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
		  0x1 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;

		nor@0,0 {
			compatible = "cfi-flash";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x0 0x0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		nand@1,0 {
			compatible = "fsl,ifc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x1 0x0 0x10000>;
		};

		cpld: board-control@2,0 {
			compatible = "fsl,ls1043ardb-cpld";
			reg = <0x2 0x0 0x0000100>;
		};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

#include "fsl-ls1043-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	ethernet@e2000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii-txid";
		status = "okay";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii-txid";
		status = "okay";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
		status = "okay";
	};

	ethernet@f0000 { /* 10GEC1 */
		phy-handle = <&aqr105_phy>;
		phy-connection-type = "xgmii";
		status = "okay";
	};

	mdio@fc000 {
		rgmii_phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		rgmii_phy2: ethernet-phy@2 {
			reg = <0x2>;
		};

		qsgmii_phy1: ethernet-phy@4 {
			reg = <0x4>;
		};

		qsgmii_phy2: ethernet-phy@5 {
			reg = <0x5>;
		};

		qsgmii_phy3: ethernet-phy@6 {
			reg = <0x6>;
		};

		qsgmii_phy4: ethernet-phy@7 {
			reg = <0x7>;
		};
	};

	mdio@fd000 {
		aqr105_phy: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c45";
			interrupts = <0 132 4>;
			reg = <0x1>;
		};
	};
};