tree 4f6322f49d1eef36f8af7e5e19297f1699e5b9a4
parent 22ff3d01348e0a2dc369b7efcbac30e4ce86d178
author Dave Liu <daveliu@freescale.com> 1227256295 +0800
committer Andrew Fleming-AFLEMING <afleming@freescale.com> 1232751794 -0600

fsl-ddr: make the self refresh idle threshold configurable

Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>