tree 1ce12817aa13a62f65562f5b9191de5956e4a892
parent c7c4fe072eeb95852f4a015df3c1a39b37caae51
author Akshay Saraswat <akshay.s@samsung.com> 1363919196 +0000
committer Minkyu Kang <mk7.kang@samsung.com> 1369135050 +0900

Exynos5: clock: Update the equation to calculate PLL output frequency

According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>