tree f16560e2a0e97630ccc49714a9f3496359ddabc7
parent d71e24950e5b2e9374cecd9655356a840917af13
author Stefan Roese <sr@denx.de> 1489156830 +0100
committer Stefan Roese <sr@denx.de> 1490262748 +0100

arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width

Tests have shown that on some boards the default width of the
configuration pulse for the PEX link detection might lead to
non-established PCIe links (link down). Especially under certain
conditions (higher temperature) and with specific PCIe devices
(in the case on the theadorable board its a Atheros PCIe WLAN
device). To enable a board-specific detection pulse width this weak
array "serdes_pex_pulse_width[4]" is introduced which can be
overwritten if needed by a board-specific version. If the board
code does not provide a non-weak version of this variable, the
default value will be used. So nothing is changed from the
current setup on the supported board.

Many thanks to Adam from Marvell for all his insights here and
his suggestion about testing with a changed detection pulse width.

Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Adam Shobash <adams@marvell.com>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>