// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 * Copyright 2017 congatec AG
 * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
 */

/dts-v1/;

/* First 128KB is for PSCI ATF. */
/memreserve/ 0x80000000 0x00020000;

#include "fsl-imx8qm.dtsi"

/ {
	model = "Congatec QMX8 Qseven series";
	compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
		stdout-path = &lpuart0;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "sw-3p3-sd1";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			off-on-delay-us = <3000>;
		};

		reg_usdhc3_vmmc: usdhc3_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "sw-3p3-sd2";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			off-on-delay-us = <3000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	fsl,rgmii_txc_dly;
	fsl,rgmii_rxc_dly;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@6 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <6>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};

&gpio2 {
	status = "okay";
};

&gpio5 {
	status = "okay";
};

&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";

	rtc_ext: m41t62@68 {
		compatible = "st,m41t62";
		reg = <0x68>;
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";

	wm8904: wm8904@1a {
		compatible = "wlf,wm8904";
		reg = <0x1a>;

		clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
		clock-names = "mclk";
		wlf,shared-lrclk;
		/* power-domains = <&pd_mclk_out0>; */

		assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
				<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
				<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
				<&clk IMX8QM_AUD_MCLKOUT0>;

		assigned-clock-rates = <786432000>, <49152000>, <24576000>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx8qm-qmx8 {

		pinctrl_hog: hoggrp{
			fsl,pins = <
				SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09		0x00000021
				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04		0x00000021
				SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08		0x00000021
				SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000021
				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15			0x00000021
				SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31		0x00000021
				SC_P_ESAI1_TX0_LSIO_GPIO2_IO08			0x00000021
				SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00		0x00000021
				SC_P_ESAI1_TX1_LSIO_GPIO2_IO09			0x00000021
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
			>;
		};

		pinctrl_lpi2c0: lpi2c0grp {
			fsl,pins = <
				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0xc600004c
				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0xc600004c
			>;
		};

		pinctrl_lpi2c1: lpi2c1grp {
			fsl,pins = <
				SC_P_GPT0_CLK_DMA_I2C1_SCL		0xc600004c
				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0xc600004c
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
			>;
		};

		pinctrl_lpuart1: lpuart1grp {
			fsl,pins = <
				SC_P_UART1_RX_DMA_UART1_RX		0x06000020
				SC_P_UART1_TX_DMA_UART1_TX		0x06000020
				SC_P_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
				SC_P_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
			>;
		};

		pinctrl_lpuart3: lpuart3grp {
			fsl,pins = <
				SC_P_M41_GPIO0_00_DMA_UART3_RX		0x06000020
				SC_P_M41_GPIO0_01_DMA_UART3_TX		0x06000020
			>;
		};

		pinctrl_mlb: mlbgrp {
			fsl,pins = <
				SC_P_MLB_SIG_CONN_MLB_SIG		0x21
				SC_P_MLB_CLK_CONN_MLB_CLK		0x21
				SC_P_MLB_DATA_CONN_MLB_DATA		0x21
			>;
		};

		pinctrl_isl29023: isl29023grp {
			fsl,pins = <
				SC_P_ADC_IN2_LSIO_GPIO3_IO20		0x00000021
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc3_gpio: usdhc3grpgpio {
			fsl,pins = <
				SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09	0x00000021
				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12	0x00000021
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000041
				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000021
				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000021
				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000021
				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000021
				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000021
				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000040
				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000020
				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000020
				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000020
				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000020
				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000020
				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
			>;
		};
	};
};

&lpuart0 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart1 { /* Q7 connector */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	status = "okay";
};

&pd_dma_lpuart0 {
	debug_console;
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc3_vmmc>;
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	status = "okay";
};