tree bfda5c57dc97c8c8f49849e572ef649ebaa2b1f5
parent 9238b52abd788cf4c2311896a5ada34ecff5499c
author Marek Vasut <marex@denx.de> 1439963209 +0200
committer Marek Vasut <marex@denx.de> 1440323781 +0200

arm: socfpga: Fix ArriaV SoCDK PLL config

Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>