tree 62db4764741b0e16415bf1bc12acbdea7f8aba24
parent a8c97f4a00fb5a9a31970351fce4355d37d19c7d
author Marek Vasut <marex@denx.de> 1587554294 +0200
committer Patrick Delaunay <patrick.delaunay@st.com> 1589439732 +0200

ARM: stm32: Implement DDR3 coding on DHCOR SoM

The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>