diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 4e2d059..2331641 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -20,6 +20,18 @@
 		u-boot,dm-pre-reloc;
 		status = "okay";
 	};
+
+	otp: nvmem@fe38c000 {
+		compatible = "rockchip,rk3568-otp";
+		reg = <0x0 0xfe38c000 0x0 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		status = "okay";
+
+		cpu_id: id@a {
+			reg = <0x0a 0x10>;
+		};
+	};
 };
 
 &combphy1 {
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 26ba9de..88be068 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -289,6 +289,8 @@
 	select DM_REGULATOR_FIXED
 	select DM_RESET
 	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_OTP
+	imply MISC_INIT_R
 	help
 	  The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
 	  including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index ebffb6c..f1f70c8 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -323,7 +323,7 @@
 #ifdef CONFIG_MISC_INIT_R
 __weak int misc_init_r(void)
 {
-	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_offset = CFG_CPUID_OFFSET;
 	const u32 cpuid_length = 0x10;
 	u8 cpuid[cpuid_length];
 	int ret;