tree 9dba3e401d9f16e48d6a9b832a00b53cb2f0111c
parent 9f481e95baaca2a5a739f930c16b1cc485b0c1f3
author Stefano Babic <sbabic@denx.de> 1282298703 +0200
committer Stefano Babic <sbabic@denx.de> 1285850534 +0200

MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51

The actual SPI driver for i.MX31 and i.MX51 controller
use a wrong byte ordering, because it is supposed
to work only with Freescale's devices, as the Power
Controllers (PMIC). The driver is not suitable for
general purposes, because the buffers passed to spi_xfer
must be 32-bit aligned, as it is used mainly to send
integer to PMIC devices.

The patch drops any kind of limitation and makes the
driver useful with devices controlled sending commands
composed by single bytes (or by a odd number of bytes), such as
spi flash, sensor, etc.

Because the byte ordering is changed,
any current driver using this controller must be adapted, too.

Signed-off-by: Stefano Babic <sbabic@denx.de>