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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 373e526e42e199bed135e8382e15aebcb6557b7b / . / arch / arm / dts / sm8250.dtsi
blob: be970472f6c4e75b5b036aec8b8b2f7c70a63b31 [file] [log] [blame]
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/clock/qcom,camcc-sm8250.h>
#include <dt-bindings/clock/qcom,videocc-sm8250.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
i2c12 = &i2c12;
i2c13 = &i2c13;
i2c14 = &i2c14;
i2c15 = &i2c15;
i2c16 = &i2c16;
i2c17 = &i2c17;
i2c18 = &i2c18;
i2c19 = &i2c19;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
spi5 = &spi5;
spi6 = &spi6;
spi7 = &spi7;
spi8 = &spi8;
spi9 = &spi9;
spi10 = &spi10;
spi11 = &spi11;
spi12 = &spi12;
spi13 = &spi13;
spi14 = &spi14;
spi15 = &spi15;
spi16 = &spi16;
spi17 = &spi17;
spi18 = &spi18;
spi19 = &spi19;
};
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-size = <0x400000>;
cache-unified;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x20000>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <444>;
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <360>;
exit-latency-us = <531>;
min-residency-us = <3934>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <702>;
exit-latency-us = <1061>;
min-residency-us = <4488>;
local-timer-stop;
};
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3264>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
};
};
};
qup_virt: interconnect-qup-virt {
compatible = "qcom,sm8250-qup-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
cpu0_opp1: opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-peak-kBps = <800000 9600000>;
};
cpu0_opp2: opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
opp-peak-kBps = <800000 9600000>;
};
cpu0_opp3: opp-518400000 {
opp-hz = /bits/ 64 <518400000>;
opp-peak-kBps = <800000 16588800>;
};
cpu0_opp4: opp-614400000 {
opp-hz = /bits/ 64 <614400000>;
opp-peak-kBps = <800000 16588800>;
};
cpu0_opp5: opp-691200000 {
opp-hz = /bits/ 64 <691200000>;
opp-peak-kBps = <800000 19660800>;
};
cpu0_opp6: opp-787200000 {
opp-hz = /bits/ 64 <787200000>;
opp-peak-kBps = <1804000 19660800>;
};
cpu0_opp7: opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-peak-kBps = <1804000 23347200>;
};
cpu0_opp8: opp-979200000 {
opp-hz = /bits/ 64 <979200000>;
opp-peak-kBps = <1804000 26419200>;
};
cpu0_opp9: opp-1075200000 {
opp-hz = /bits/ 64 <1075200000>;
opp-peak-kBps = <1804000 29491200>;
};
cpu0_opp10: opp-1171200000 {
opp-hz = /bits/ 64 <1171200000>;
opp-peak-kBps = <1804000 32563200>;
};
cpu0_opp11: opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-peak-kBps = <1804000 36249600>;
};
cpu0_opp12: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <2188000 36249600>;
};
cpu0_opp13: opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <2188000 39321600>;
};
cpu0_opp14: opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <3072000 42393600>;
};
cpu0_opp15: opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <3072000 42393600>;
};
cpu0_opp16: opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <4068000 42393600>;
};
cpu0_opp17: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <4068000 42393600>;
};
};
cpu4_opp_table: opp-table-cpu4 {
compatible = "operating-points-v2";
opp-shared;
cpu4_opp1: opp-710400000 {
opp-hz = /bits/ 64 <710400000>;
opp-peak-kBps = <1804000 19660800>;
};
cpu4_opp2: opp-825600000 {
opp-hz = /bits/ 64 <825600000>;
opp-peak-kBps = <2188000 23347200>;
};
cpu4_opp3: opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
opp-peak-kBps = <2188000 26419200>;
};
cpu4_opp4: opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-peak-kBps = <3072000 26419200>;
};
cpu4_opp5: opp-1171200000 {
opp-hz = /bits/ 64 <1171200000>;
opp-peak-kBps = <3072000 29491200>;
};
cpu4_opp6: opp-1286400000 {
opp-hz = /bits/ 64 <1286400000>;
opp-peak-kBps = <4068000 29491200>;
};
cpu4_opp7: opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-peak-kBps = <4068000 32563200>;
};
cpu4_opp8: opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
opp-peak-kBps = <4068000 32563200>;
};
cpu4_opp9: opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <5412000 39321600>;
};
cpu4_opp10: opp-1670400000 {
opp-hz = /bits/ 64 <1670400000>;
opp-peak-kBps = <5412000 42393600>;
};
cpu4_opp11: opp-1766400000 {
opp-hz = /bits/ 64 <1766400000>;
opp-peak-kBps = <5412000 45465600>;
};
cpu4_opp12: opp-1862400000 {
opp-hz = /bits/ 64 <1862400000>;
opp-peak-kBps = <6220000 45465600>;
};
cpu4_opp13: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <6220000 48537600>;
};
cpu4_opp14: opp-2054400000 {
opp-hz = /bits/ 64 <2054400000>;
opp-peak-kBps = <7216000 48537600>;
};
cpu4_opp15: opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
opp-peak-kBps = <7216000 51609600>;
};
cpu4_opp16: opp-2246400000 {
opp-hz = /bits/ 64 <2246400000>;
opp-peak-kBps = <7216000 51609600>;
};
cpu4_opp17: opp-2342400000 {
opp-hz = /bits/ 64 <2342400000>;
opp-peak-kBps = <8368000 51609600>;
};
cpu4_opp18: opp-2419200000 {
opp-hz = /bits/ 64 <2419200000>;
opp-peak-kBps = <8368000 51609600>;
};
};
cpu7_opp_table: opp-table-cpu7 {
compatible = "operating-points-v2";
opp-shared;
cpu7_opp1: opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
opp-peak-kBps = <2188000 19660800>;
};
cpu7_opp2: opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <2188000 26419200>;
};
cpu7_opp3: opp-1075200000 {
opp-hz = /bits/ 64 <1075200000>;
opp-peak-kBps = <3072000 26419200>;
};
cpu7_opp4: opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <3072000 29491200>;
};
cpu7_opp5: opp-1305600000 {
opp-hz = /bits/ 64 <1305600000>;
opp-peak-kBps = <4068000 32563200>;
};
cpu7_opp6: opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-peak-kBps = <4068000 32563200>;
};
cpu7_opp7: opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <4068000 36249600>;
};
cpu7_opp8: opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
opp-peak-kBps = <5412000 39321600>;
};
cpu7_opp9: opp-1747200000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <5412000 42393600>;
};
cpu7_opp10: opp-1862400000 {
opp-hz = /bits/ 64 <1862400000>;
opp-peak-kBps = <6220000 45465600>;
};
cpu7_opp11: opp-1977600000 {
opp-hz = /bits/ 64 <1977600000>;
opp-peak-kBps = <6220000 48537600>;
};
cpu7_opp12: opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
opp-peak-kBps = <7216000 48537600>;
};
cpu7_opp13: opp-2169600000 {
opp-hz = /bits/ 64 <2169600000>;
opp-peak-kBps = <7216000 51609600>;
};
cpu7_opp14: opp-2265600000 {
opp-hz = /bits/ 64 <2265600000>;
opp-peak-kBps = <7216000 51609600>;
};
cpu7_opp15: opp-2361600000 {
opp-hz = /bits/ 64 <2361600000>;
opp-peak-kBps = <8368000 51609600>;
};
cpu7_opp16: opp-2457600000 {
opp-hz = /bits/ 64 <2457600000>;
opp-peak-kBps = <8368000 51609600>;
};
cpu7_opp17: opp-2553600000 {
opp-hz = /bits/ 64 <2553600000>;
opp-peak-kBps = <8368000 51609600>;
};
cpu7_opp18: opp-2649600000 {
opp-hz = /bits/ 64 <2649600000>;
opp-peak-kBps = <8368000 51609600>;
};
cpu7_opp19: opp-2745600000 {
opp-hz = /bits/ 64 <2745600000>;
opp-peak-kBps = <8368000 51609600>;
};
cpu7_opp20: opp-2841600000 {
opp-hz = /bits/ 64 <2841600000>;
opp-peak-kBps = <8368000 51609600>;
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8250", "qcom,scm";
#reset-cells = <1>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
};
qup_opp_table: opp-table-qup {
compatible = "operating-points-v2";
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-120000000 {
opp-hz = /bits/ 64 <120000000>;
required-opps = <&rpmhpd_opp_svs>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: memory@80000000 {
reg = <0x0 0x80000000 0x0 0x600000>;
no-map;
};
xbl_aop_mem: memory@80700000 {
reg = <0x0 0x80700000 0x0 0x160000>;
no-map;
};
cmd_db: memory@80860000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x80860000 0x0 0x20000>;
no-map;
};
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
};
removed_mem: memory@80b00000 {
reg = <0x0 0x80b00000 0x0 0x5300000>;
no-map;
};
camera_mem: memory@86200000 {
reg = <0x0 0x86200000 0x0 0x500000>;
no-map;
};
wlan_mem: memory@86700000 {
reg = <0x0 0x86700000 0x0 0x100000>;
no-map;
};
ipa_fw_mem: memory@86800000 {
reg = <0x0 0x86800000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: memory@86810000 {
reg = <0x0 0x86810000 0x0 0xa000>;
no-map;
};
gpu_mem: memory@8681a000 {
reg = <0x0 0x8681a000 0x0 0x2000>;
no-map;
};
npu_mem: memory@86900000 {
reg = <0x0 0x86900000 0x0 0x500000>;
no-map;
};
video_mem: memory@86e00000 {
reg = <0x0 0x86e00000 0x0 0x500000>;
no-map;
};
cvp_mem: memory@87300000 {
reg = <0x0 0x87300000 0x0 0x500000>;
no-map;
};
cdsp_mem: memory@87800000 {
reg = <0x0 0x87800000 0x0 0x1400000>;
no-map;
};
slpi_mem: memory@88c00000 {
reg = <0x0 0x88c00000 0x0 0x1500000>;
no-map;
};
adsp_mem: memory@8a100000 {
reg = <0x0 0x8a100000 0x0 0x1d00000>;
no-map;
};
spss_mem: memory@8be00000 {
reg = <0x0 0x8be00000 0x0 0x100000>;
no-map;
};
cdsp_secure_heap: memory@8bf00000 {
reg = <0x0 0x8bf00000 0x0 0x4600000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
smp2p_slpi_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_slpi_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sm8250";
reg = <0x0 0x00100000 0x0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
};
ipcc: mailbox@408000 {
compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
reg = <0 0x00408000 0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
qfprom: efuse@784000 {
compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@19b {
reg = <0x19b 0x1>;
bits = <5 3>;
};
};
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0 0x00793000 0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0x00800000 0 0x70000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <10>;
dma-channel-mask = <0x3f>;
iommus = <&apps_smmu 0x76 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
iommus = <&apps_smmu 0x63 0x0>;
ranges;
status = "disabled";
i2c14: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c14_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi14: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c15: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c15_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi15: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c16: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c16_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi16: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c17: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c17_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi17: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart17: serial@88c000 {
compatible = "qcom,geni-uart";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart17_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c18_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi18: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart18: serial@890000 {
compatible = "qcom,geni-uart";
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart18_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
i2c19: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c19_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi19: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma0: dma-controller@900000 {
compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0x00900000 0 0x70000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <15>;
dma-channel-mask = <0x7ff>;
iommus = <&apps_smmu 0x5b6 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
iommus = <&apps_smmu 0x5a3 0x0>;
ranges;
status = "disabled";
i2c0: i2c@980000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00980000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@980000 {
compatible = "qcom,geni-spi";
reg = <0 0x00980000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@984000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00984000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@984000 {
compatible = "qcom,geni-spi";
reg = <0 0x00984000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@988000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00988000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@988000 {
compatible = "qcom,geni-spi";
reg = <0 0x00988000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@988000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00988000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
i2c3: i2c@98c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0098c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@98c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0098c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@990000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00990000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@990000 {
compatible = "qcom,geni-spi";
reg = <0 0x00990000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@994000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@994000 {
compatible = "qcom,geni-spi";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@998000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00998000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@998000 {
compatible = "qcom,geni-spi";
reg = <0 0x00998000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart6: serial@998000 {
compatible = "qcom,geni-uart";
reg = <0 0x00998000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
i2c7: i2c@99c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0099c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi7: spi@99c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0099c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0x00a00000 0 0x70000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <10>;
dma-channel-mask = <0x3f>;
iommus = <&apps_smmu 0x56 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
iommus = <&apps_smmu 0x43 0x0>;
ranges;
status = "disabled";
i2c8: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart12: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
interconnect-names = "qup-core",
"qup-config";
status = "disabled";
};
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi13: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
config_noc: interconnect@1500000 {
compatible = "qcom,sm8250-config-noc";
reg = <0 0x01500000 0 0xa580>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sm8250-system-noc";
reg = <0 0x01620000 0 0x1c200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@163d000 {
compatible = "qcom,sm8250-mc-virt";
reg = <0 0x0163d000 0 0x1000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8250-aggre1-noc";
reg = <0 0x016e0000 0 0x1f180>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm8250-aggre2-noc";
reg = <0 0x01700000 0 0x33000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@1733000 {
compatible = "qcom,sm8250-compute-noc";
reg = <0 0x01733000 0 0xa180>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sm8250-mmss-noc";
reg = <0 0x01740000 0 0x1f080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie0: pci@1c00000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
<0 0x60100000 0 0x100000>,
<0 0x01c03000 0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"tbu",
"ddrss_sf_tbu";
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
dma-coherent;
status = "disabled";
};
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
reg = <0 0x01c06000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_WIFI_CLKREF_EN>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
pcie1: pci@1c08000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
<0 0x40001000 0 0x1000>,
<0 0x40100000 0 0x100000>,
<0 0x01c0b000 0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"ref",
"tbu",
"ddrss_sf_tbu";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
dma-coherent;
status = "disabled";
};
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
reg = <0 0x01c0e000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
pcie2: pci@1c10000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>,
<0 0x64000f20 0 0xa8>,
<0 0x64001000 0 0x1000>,
<0 0x64100000 0 0x100000>,
<0 0x01c13000 0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_MDM_CLKREF_EN>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"ref",
"tbu",
"ddrss_sf_tbu";
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
<0x100 &apps_smmu 0x1d01 0x1>;
resets = <&gcc GCC_PCIE_2_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_2_GDSC>;
phys = <&pcie2_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
dma-coherent;
status = "disabled";
};
pcie2_phy: phy@1c16000 {
compatible = "qcom,sm8250-qmp-modem-pcie-phy";
reg = <0 0x01c16000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MDM_CLKREF_EN>,
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
clock-output-names = "pcie_2_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<37500000 300000000>,
<0 0>,
<0 0>,
<37500000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs";
status = "disabled";
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8250-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x16c>,
<0 0x01d87600 0 0x200>,
<0 0x01d87c00 0 0x200>,
<0 0x01d87800 0 0x16c>,
<0 0x01d87a00 0 0x200>;
#phy-cells = <0>;
};
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x24000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <8>;
qcom,num-ees = <2>;
iommus = <&apps_smmu 0x592 0x0000>,
<&apps_smmu 0x598 0x0000>,
<&apps_smmu 0x599 0x0000>,
<&apps_smmu 0x59f 0x0000>,
<&apps_smmu 0x586 0x0011>,
<&apps_smmu 0x596 0x0011>;
};
crypto: crypto@1dfa000 {
compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0 0x01dfa000 0 0x6000>;
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x592 0x0000>,
<&apps_smmu 0x598 0x0000>,
<&apps_smmu 0x599 0x0000>,
<&apps_smmu 0x59f 0x0000>,
<&apps_smmu 0x586 0x0011>,
<&apps_smmu 0x596 0x0011>;
interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "memory";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
wsamacro: codec@3240000 {
compatible = "qcom,sm8250-lpass-wsa-macro";
reg = <0 0x03240000 0 0x1000>;
clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
<&audiocc LPASS_CDC_WSA_NPL>,
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&aoncc LPASS_CDC_VA_MCLK>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&wsa_swr_active>;
status = "disabled";
};
swr0: soundwire-controller@3250000 {
reg = <0 0x03250000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wsamacro>;
clock-names = "iface";
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
#sound-dai-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
status = "disabled";
};
audiocc: clock-controller@3300000 {
compatible = "qcom,sm8250-lpass-audiocc";
reg = <0 0x03300000 0 0x30000>;
#clock-cells = <1>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio", "bus";
};
vamacro: codec@3370000 {
compatible = "qcom,sm8250-lpass-va-macro";
reg = <0 0x03370000 0 0x1000>;
clocks = <&aoncc LPASS_CDC_VA_MCLK>,
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "macro", "dcodec";
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
};
rxmacro: rxmacro@3200000 {
pinctrl-names = "default";
pinctrl-0 = <&rx_swr_active>;
compatible = "qcom,sm8250-lpass-rx-macro";
reg = <0 0x03200000 0 0x1000>;
status = "disabled";
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
swr1: soundwire-controller@3210000 {
reg = <0 0x03210000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
status = "disabled";
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rxmacro>;
clock-names = "iface";
label = "RX";
qcom,din-ports = <0>;
qcom,dout-ports = <5>;
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
#sound-dai-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
};
txmacro: txmacro@3220000 {
pinctrl-names = "default";
pinctrl-0 = <&tx_swr_active>;
compatible = "qcom,sm8250-lpass-tx-macro";
reg = <0 0x03220000 0 0x1000>;
status = "disabled";
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
/* tx macro */
swr2: soundwire-controller@3230000 {
reg = <0 0x03230000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core";
status = "disabled";
clocks = <&txmacro>;
clock-names = "iface";
label = "TX";
qcom,din-ports = <5>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
#sound-dai-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
};
aoncc: clock-controller@3380000 {
compatible = "qcom,sm8250-lpass-aoncc";
reg = <0 0x03380000 0 0x40000>;
#clock-cells = <1>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio", "bus";
};
lpass_tlmm: pinctrl@33c0000 {
compatible = "qcom,sm8250-lpass-lpi-pinctrl";
reg = <0 0x033c0000 0x0 0x20000>,
<0 0x03550000 0x0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 14>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
wsa_swr_active: wsa-swr-active-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
wsa_swr_sleep: wsa-swr-sleep-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
bias-pull-down;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
bias-pull-down;
};
};
dmic01_active: dmic01-active-state {
clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
};
};
dmic01_sleep: dmic01-sleep-state {
clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <2>;
bias-disable;
output-low;
};
data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <2>;
bias-pull-down;
};
};
rx_swr_active: rx-swr-active-state {
clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};