// SPDX-License-Identifier: GPL-2.0+
/*
 *(C) Copyright 2019 Rockchip Electronics Co., Ltd
 */

#include "rockchip-u-boot.dtsi"

/ {
	aliases {
		mmc0 = &emmc;
		mmc1 = &sdmmc;
	};

	chosen {
		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
	};

	dmc: dmc@ff010000 {
		compatible = "rockchip,rk3308-dmc";
		reg = <0x0 0xff010000 0x0 0x10000>;
		bootph-all;
	};

	otp: nvmem@ff210000 {
		compatible = "rockchip,rk3308-otp";
		reg = <0x0 0xff210000 0x0 0x4000>;
		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
			 <&cru PCLK_OTP_PHY>;
		clock-names = "otp", "apb_pclk", "phy";
		resets = <&cru SRST_OTP_PHY>;
		reset-names = "phy";
		#address-cells = <1>;
		#size-cells = <1>;

		cpu_id: id@7 {
			reg = <0x07 0x10>;
		};
	};

	rng: rng@ff2f0000 {
		compatible = "rockchip,cryptov2-rng";
		reg = <0x0 0xff2f0000 0x0 0x4000>;
	};
};

&cru {
	bootph-all;
};

&emmc {
	bootph-pre-ram;
	bootph-some-ram;

	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
	u-boot,spl-fifo-mode;
};

&emmc_bus8 {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_clk {
	bootph-pre-ram;
	bootph-some-ram;
};

&emmc_cmd {
	bootph-pre-ram;
	bootph-some-ram;
};

&grf {
	bootph-all;
};

&pcfg_pull_none {
	bootph-all;
};

&pcfg_pull_none_4ma {
	bootph-pre-ram;
	bootph-some-ram;
};

&pcfg_pull_none_8ma {
	bootph-pre-ram;
	bootph-some-ram;
};

&pcfg_pull_up {
	bootph-all;
};

&pcfg_pull_up_4ma {
	bootph-pre-ram;
	bootph-some-ram;
};

&pcfg_pull_up_8ma {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl {
	bootph-all;
};

&rtc_32k {
	bootph-all;
};

&sdmmc {
	bootph-pre-ram;
	bootph-some-ram;

	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
	u-boot,spl-fifo-mode;
};

&sdmmc_bus4 {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_clk {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_cmd {
	bootph-pre-ram;
	bootph-some-ram;
};

&sdmmc_det {
	bootph-pre-ram;
	bootph-some-ram;
};

&xin24m {
	bootph-all;
};