tree ec370646297026107f4d3d5865648546945e7e05
parent a6a77e47343d0b511136b76da0c853304a3f1423
author Samuel Holland <samuel@sholland.org> 1698730541 -0500
committer Leo Yu-Chi Liang <ycliang@andestech.com> 1698909346 +0800

riscv: Align the trap handler to 64 bytes

This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>