tree e481fe5e4eed432724f4891497b7c026cef938ec
parent 64e8482f1c94ab6e1fb4837a8744ca8a156c507e
author Zong Li <zong.li@sifive.com> 1702562977 +0000
committer Leo Yu-Chi Liang <ycliang@andestech.com> 1703669337 +0800

riscv: cache: support cache enable in SPL stage

The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>