tree b2cd09665f2813bd3f5de81840c9979f85f77347
parent 9ca2116ce49449602eb9e2f8a0cafe811bcc3086
author Marek Vasut <marex@denx.de> 1410737348 +0200
committer Marek Vasut <marex@denx.de> 1412610410 +0200

arm: socfpga: cache: Enable D-Cache

The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>