tree 07118135410c7b399c8ac780b6fa803ceebdfaea
parent 94025b1cd8d9959ebf987a7f6382d513c606ecf1
author Stephen George <stephen.george@freescale.com> 1364197212 +0000
committer Andy Fleming <afleming@freescale.com> 1369432452 -0500

board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M

Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>