tree 0685aeabf6c3c141279b3f96e32c46c45ab55904
parent bee61801264988d4250e8536bf62336621d2e9fb
author Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 1498168424 +0200
committer Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 1502637152 +0200

rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM

The RK3368 has a somewhat temperamental BootROM (which I learned the
hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
experiments show that changing the GPLL broke things for me, while
changing the CPLL seems to be more benign).  These should not be
modified by the SPL stage, if we intend to return to the BootROM for
chain booting the next stage.

This commit changes the clock initialisation to not change CPLL/GPLL
before returning to the BootROM (i.e. in TPL).  As it's safe to change
these settings if we no longer intend to return to U-Boot, we'll run
the full PLL setup a little later (i.e. in SPL).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>