Merge branch 'master' into next
Merge in v2022.07-rc5.
diff --git a/Kconfig b/Kconfig
index f7e3c33..429b5f9 100644
--- a/Kconfig
+++ b/Kconfig
@@ -228,12 +228,38 @@
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
+config SYS_BARGSIZE
+ int "Size of kernel command line buffer in bytes"
+ depends on SYS_BOOT_GET_CMDLINE
+ default 512
+ help
+ Buffer size for Boot Arguments which are passed to the application
+ (usually a Linux kernel) when it is booted
+
config SYS_BOOT_GET_KBD
bool "Enable kernel board information setup"
help
Enables allocating and saving a kernel copy of the bd_info in
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+config HAS_CUSTOM_SYS_INIT_SP_ADDR
+ bool "Use a custom location for the initial stack pointer address"
+ depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
+ default y if TFABOOT
+ help
+ Typically, we use an initial stack pointer address that is calculated
+ by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
+ statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
+ build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different
+ but statica calculation is performed. However, some platforms will
+ take a different approach. Say Y here to define the address statically
+ instead.
+
+config CUSTOM_SYS_INIT_SP_ADDR
+ hex "Static location for the initial stack pointer"
+ depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
+ default SYS_TEXT_BASE if TFABOOT
+
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default y if DM
diff --git a/MAINTAINERS b/MAINTAINERS
index 28e4d38..2ebec1f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -206,6 +206,17 @@
F: configs/rpi_*
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
+ARM BROADCOM BCMBCA
+M: Anand Gore <anand.gore@broadcom.com>
+M: William Zhang <william.zhang@broadcom.com>
+M: Kursad Oney <kursad.oney@broadcom.com>
+M: Joel Peshkin <joel.peshkin@broadcom.com>
+S: Maintained
+F: arch/arm/mach-bcmbca/
+F: board/broadcom/bcmbca/
+F: configs/bcm947622_defconfig
+F: include/configs/bcm947622.h
+
ARM BROADCOM BCMSTB
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
S: Maintained
@@ -282,6 +293,11 @@
F: drivers/net/mdio-ipq4019.c
F: drivers/rng/msm_rng.c
+ARM LAYERSCAPE SFP
+M: Sean Anderson <sean.anderson@seco.com>
+S: Maintained
+F: drivers/misc/ls2_sfp.c
+
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
S: Maintained
@@ -480,7 +496,7 @@
F: arch/arm/mach-stm32mp/
F: doc/board/st/
F: drivers/adc/stm32-adc*
-F: drivers/clk/clk_stm32mp1.c
+F: drivers/clk/stm32/
F: drivers/gpio/stm32_gpio.c
F: drivers/hwspinlock/stm32_hwspinlock.c
F: drivers/i2c/stm32f7_i2c.c
@@ -1091,6 +1107,13 @@
F: include/nvme.h
F: doc/develop/driver-model/nvme.rst
+NVMEM
+M: Sean Anderson <seanga2@gmail.com>
+S: Maintained
+F: doc/api/nvmem.rst
+F: drivers/misc/nvmem.c
+F: include/nvmem.h
+
NXP C45 TJA11XX PHY DRIVER
M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
S: Maintained
diff --git a/README b/README
index b7ab6e5..9800359 100644
--- a/README
+++ b/README
@@ -293,33 +293,6 @@
SPL-specific notes:
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
- CONFIG_SPL_STACK_R_ADDR points into SDRAM
- - preloader_console_init() can be called here - typically this is
- done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
- spl_board_init() function containing this call
- - loads U-Boot or (in falcon mode) Linux
-
-
-Configuration Options:
-----------------------
-
-Configuration depends on the combination of board and CPU type; all
-such information is kept in a configuration file
-"include/configs/<board_name>.h".
-
-Example: For a TQM823L module, all configuration settings are in
-"include/configs/TQM823L.h".
-
-
-Many of the options are named exactly as the corresponding Linux
-kernel configuration options. The intention is to make it easier to
-build a config tool - later.
-
-- ARM Platform Bus Type(CCI):
- CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
- provides full cache coherency between two clusters of multi-core
- CPUs and I/O coherency for devices and I/O masters
-
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
@@ -493,12 +466,6 @@
Defines the SEC controller register space as Little Endian
- MIPS CPU options:
- CONFIG_SYS_INIT_SP_OFFSET
-
- Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
- pointer. This is needed for the temporary stack before
- relocation.
-
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
@@ -1658,36 +1625,6 @@
CONFIG_SPL
Enable building of SPL globally.
- CONFIG_SPL_MAX_FOOTPRINT
- Maximum size in memory allocated to the SPL, BSS included.
- When defined, the linker checks that the actual memory
- used by SPL from _start to __bss_end does not exceed it.
- CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
- must not be both defined at the same time.
-
- CONFIG_SPL_MAX_SIZE
- Maximum size of the SPL image (text, data, rodata, and
- linker lists sections), BSS excluded.
- When defined, the linker checks that the actual size does
- not exceed it.
-
- CONFIG_SPL_RELOC_TEXT_BASE
- Address to relocate to. If unspecified, this is equal to
- CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
-
- CONFIG_SPL_BSS_START_ADDR
- Link address for the BSS within the SPL binary.
-
- CONFIG_SPL_BSS_MAX_SIZE
- Maximum size in memory allocated to the SPL BSS.
- When defined, the linker checks that the actual memory used
- by SPL from __bss_start to __bss_end does not exceed it.
- CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
- must not be both defined at the same time.
-
- CONFIG_SPL_STACK
- Adress of the start of the stack SPL will use
-
CONFIG_SPL_PANIC_ON_RAW_IMAGE
When defined, SPL will panic() if the image it has
loaded does not have a signature.
@@ -1698,65 +1635,20 @@
consider that a completely unreadable NAND block is bad,
and thus should be skipped silently.
- CONFIG_SPL_RELOC_STACK
- Adress of the start of the stack SPL will use after
- relocation. If unspecified, this is equal to
- CONFIG_SPL_STACK.
-
- CONFIG_SYS_SPL_MALLOC_START
- Starting address of the malloc pool used in SPL.
- When this option is set the full malloc is used in SPL and
- it is set up by spl_init() and before that, the simple malloc()
- can be used if CONFIG_SYS_MALLOC_F is defined.
-
- CONFIG_SYS_SPL_MALLOC_SIZE
- The size of the malloc pool used in SPL.
-
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
- CONFIG_SPL_INIT_MINIMAL
- Arch init code should be built for a very small image
-
- CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
- CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
- Sector and number of sectors to load kernel argument
- parameters from when MMC is being used in raw mode
- (for falcon mode)
-
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- Filename to read to load U-Boot when reading from filesystem
-
- CONFIG_SPL_FS_LOAD_KERNEL_NAME
- Filename to read to load kernel uImage when reading
- from filesystem (for Falcon mode)
-
- CONFIG_SPL_FS_LOAD_ARGS_NAME
- Filename to read to load kernel argument parameters
- when reading from filesystem (for Falcon mode)
-
CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
Set this for NAND SPL on PPC mpc83xx targets, so that
start.S waits for the rest of the SPL to load before
continuing (the hardware starts execution after just
loading the first page rather than the full 4K).
- CONFIG_SPL_SKIP_RELOCATE
- Avoid SPL relocation
-
CONFIG_SPL_UBI
Support for a lightweight UBI (fastmap) scanner and
loader
- CONFIG_SPL_NAND_RAW_ONLY
- Support to boot only raw u-boot.bin images. Use this only
- if you need to save space.
-
- CONFIG_SPL_COMMON_INIT_DDR
- Set for common ddr init with serial presence detect in
- SPL binary.
-
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@@ -1781,35 +1673,12 @@
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
- CONFIG_SPL_PAD_TO
- Image offset to which the SPL should be padded before appending
- the SPL payload. By default, this is defined as
- CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
- CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
- payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-
- CONFIG_SPL_TARGET
- Final target image containing SPL and payload. Some SPLs
- use an arch-specific makefile fragment instead, for
- example if more than one image needs to be produced.
-
CONFIG_SPL_FIT_PRINT
Printing information about a FIT image adds quite a bit of
code to SPL. So this is normally disabled in SPL. Use this
option to re-enable it. This will affect the output of the
bootm command when booting a FIT image.
-- TPL framework
- CONFIG_TPL
- Enable building of TPL globally.
-
- CONFIG_TPL_PAD_TO
- Image offset to which the TPL should be padded before appending
- the TPL payload. By default, this is defined as
- CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
- CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
- payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
-
- Interrupt support (PPC):
There are common interrupt_init() and timer_interrupt()
@@ -1853,16 +1722,6 @@
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
-- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
-
-- CONFIG_SYS_PBSIZE: Buffer size for Console output
-
-- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
-
-- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
- the application (usually a Linux kernel) when it is
- booted
-
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
@@ -1909,7 +1768,7 @@
- CONFIG_SYS_MALLOC_SIMPLE
Provides a simple and small malloc() and calloc() for those
boards which do not use the full malloc in SPL (which is
- enabled with CONFIG_SYS_SPL_MALLOC_START).
+ enabled with CONFIG_SYS_SPL_MALLOC).
- CONFIG_SYS_NONCACHED_MEMORY:
Size of non-cached memory area. This area of memory will be
@@ -2186,10 +2045,6 @@
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
-- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
- If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
- forced to a value that ensures that CCSR is not relocated.
-
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
@@ -2207,24 +2062,6 @@
U-Boot uses the following memory types:
- MPC8xx: IMMR (internal memory of the CPU)
-- CONFIG_SYS_GBL_DATA_OFFSET:
-
- Offset of the initial data structure in the memory
- area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
- CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
- data is located at the end of the available space
- (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
- GENERATED_GBL_DATA_SIZE), and the initial stack is just
- below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
- CONFIG_SYS_GBL_DATA_OFFSET) downward.
-
- Note:
- On the MPC824X (or other systems that use the data
- cache for initial memory) the address chosen for
- CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
- point to an otherwise UNUSED address space between
- the top of RAM and the start of the PCI space.
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
diff --git a/arch/Kconfig b/arch/Kconfig
index 12de8a1..b396263 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -371,6 +371,9 @@
default 0xF0000000 if ARCH_MPC8313
default 0xE0000000 if MPC83xx && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
+ ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
+ ARCH_P2020
default SYS_CCSRBAR_DEFAULT
help
Address for the Internal Memory-Mapped Registers (IMMR) window used
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 016ae85..9f5547e 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -7,6 +7,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/arcregs.h>
+#include <system-constants.h>
ENTRY(_start)
/* Setup interrupt vector base that matches "__text_start" */
@@ -86,7 +87,7 @@
#endif
/* Establish C runtime stack and frame */
- mov %sp, CONFIG_SYS_INIT_SP_ADDR
+ mov %sp, SYS_INIT_SP_ADDR
mov %fp, %sp
/* Allocate reserved area from current top of stack */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9898c7d..c618aad 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -718,6 +718,11 @@
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
+config ARCH_BCMBCA
+ bool "Broadcom broadband chip family"
+ select DM
+ select OF_CONTROL
+
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
@@ -1923,7 +1928,7 @@
imply CMD_DM
config ARCH_STI
- bool "Support STMicrolectronics SoCs"
+ bool "Support STMicroelectronics SoCs"
select BLK
select CPU_V7A
select DM
@@ -1951,7 +1956,6 @@
select OF_SYSTEM_SETUP
select PINCTRL
select REGMAP
- select SUPPORT_SPL
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
@@ -2187,6 +2191,8 @@
source "arch/arm/mach-bcm283x/Kconfig"
+source "arch/arm/mach-bcmbca/Kconfig"
+
source "arch/arm/mach-bcmstb/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 85c23bc..a342d72 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -59,6 +59,7 @@
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
+machine-$(CONFIG_ARCH_BCMBCA) += bcmbca
machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_EXYNOS) += exynos
@@ -103,8 +104,8 @@
head-y := arch/arm/cpu/$(CPU)/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq ($(CONFIG_SPL_START_S_PATH),)
-head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
+head-y := arch/arm/cpu/arm926ejs/mxs/start.o
endif
endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S
index adec2c8..61982e3 100644
--- a/arch/arm/cpu/arm926ejs/mxs/start.S
+++ b/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -21,6 +21,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
+#include <system-constants.h>
/*
*************************************************************************
@@ -44,7 +45,7 @@
* it point to the end of OCRAM if the SP is zero.
*/
cmp sp, #0x00000000
- ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
+ ldreq sp, =SYS_INIT_SP_ADDR
/*
* Store all registers on old stack pointer, this will allow us later to
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index ba4b374..3c8c07f 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -13,6 +13,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
+#include <system-constants.h>
.pushsection .text.s_init, "ax"
WEAK(s_init)
@@ -28,7 +29,7 @@
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =CONFIG_SPL_STACK
#else
- ldr sp, =CONFIG_SYS_INIT_SP_ADDR
+ ldr sp, =SYS_INIT_SP_ADDR
#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_SPL_DM
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 3703612..4f6327f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -17,6 +17,7 @@
#include <asm/system.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
+#include <system-constants.h>
/*************************************************************************
*
@@ -254,7 +255,7 @@
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
- ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
+ ldr r0, =(SYS_INIT_SP_ADDR)
#endif
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0
diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S
index 218ac70..5733eaa1 100644
--- a/arch/arm/cpu/armv7/stv0991/lowlevel.S
+++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2014 stmicroelectronics
+ * (C) Copyright 2014 STMicroelectronics
*/
#include <config.h>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 570105a..840e6d4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -29,8 +29,8 @@
* mux 2 clock for LS1043A/LS1046A.
*/
#if defined(CONFIG_SYS_DPAA_FMAN) || \
- defined(CONFIG_TARGET_LS1046ARDB) || \
- defined(CONFIG_TARGET_LS1043ARDB)
+ defined(CONFIG_ARCH_LS1046A) || \
+ defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -129,13 +129,13 @@
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
-#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
+#if defined(CONFIG_ARCH_LS1046A) || defined(CONFIG_ARCH_LS1043A)
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
case 1:
sys_info->freq_cga_m2 = freq_c_pll[1];
break;
-#if defined(CONFIG_TARGET_LS1046ARDB)
+#if defined(CONFIG_ARCH_LS1046A)
case 2:
sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
break;
@@ -143,7 +143,7 @@
case 3:
sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
break;
-#if defined(CONFIG_TARGET_LS1046ARDB)
+#if defined(CONFIG_ARCH_LS1046A)
case 6:
sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
break;
diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index 263d9dd..fab7732 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -5,7 +5,6 @@
extra-y = start.o
-obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o
obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o
obj-y += cpuinfo.o
diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c
index 0d9542f..549b61d 100644
--- a/arch/arm/cpu/pxa/cpuinfo.c
+++ b/arch/arm/cpu/pxa/cpuinfo.c
@@ -11,12 +11,6 @@
#include <errno.h>
#include <linux/compiler.h>
-#ifdef CONFIG_CPU_PXA25X
-#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
-#error "Init SP address must be set to 0xfffff800 for PXA250"
-#endif
-#endif
-
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 896e05f..ab7bcb4 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -49,9 +49,6 @@
bl cpu_init_crit
#endif
-#ifdef CONFIG_CPU_PXA25X
- bl lock_cache_for_stack
-#endif
#ifdef CONFIG_CPU_PXA27X
/*
* enable clock for SRAM
@@ -67,20 +64,7 @@
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
-
-#ifdef CONFIG_CPU_PXA25X
- /*
- * Unlock (actually, disable) the cache now that board_init_f
- * is done. We could do this earlier but we would need to add
- * a new C runtime hook, whereas c_runtime_cpu_setup already
- * exists.
- * As this routine is just a call to cpu_init_crit, let us
- * tail-optimize and do a simple branch here.
- */
- b cpu_init_crit
-#else
bx lr
-#endif
/*
*************************************************************************
@@ -92,7 +76,7 @@
*
*************************************************************************
*/
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@@ -111,95 +95,4 @@
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
-#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
-
-/*
- * Enable MMU to use DCache as DRAM.
- *
- * This is useful on PXA25x and PXA26x in early bootstages, where there is no
- * other possible memory available to hold stack.
- */
-#ifdef CONFIG_CPU_PXA25X
-.macro CPWAIT reg
- mrc p15, 0, \reg, c2, c0, 0
- mov \reg, \reg
- sub pc, pc, #4
-.endm
-lock_cache_for_stack:
- /* Domain access -- enable for all CPs */
- ldr r0, =0x0000ffff
- mcr p15, 0, r0, c3, c0, 0
-
- /* Point TTBR to MMU table */
- ldr r0, =mmutable
- mcr p15, 0, r0, c2, c0, 0
-
- /* Kick in MMU, ICache, DCache, BTB */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, #0x1b00
- bic r0, #0x0087
- orr r0, #0x1800
- orr r0, #0x0005
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* Unlock Icache, Dcache */
- mcr p15, 0, r0, c9, c1, 1
- mcr p15, 0, r0, c9, c2, 1
-
- /* Flush Icache, Dcache, BTB */
- mcr p15, 0, r0, c7, c7, 0
-
- /* Unlock I-TLB, D-TLB */
- mcr p15, 0, r0, c10, c4, 1
- mcr p15, 0, r0, c10, c8, 1
-
- /* Flush TLB */
- mcr p15, 0, r0, c8, c7, 0
-
- /* Allocate 4096 bytes of Dcache as RAM */
-
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
-
- mov r4, #0x00
- mov r5, #0x00
- mov r2, #0x01
- mcr p15, 0, r0, c9, c2, 0
- CPWAIT r0
-
- /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
- mov r0, #128
- ldr r1, =0xfffff000
-
-alloc:
- mcr p15, 0, r1, c7, c2, 5
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
- strd r4, [r1], #8
- strd r4, [r1], #8
- strd r4, [r1], #8
- strd r4, [r1], #8
- subs r0, #0x01
- bne alloc
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
- mov r2, #0x00
- mcr p15, 0, r2, c9, c2, 0
- CPWAIT r0
-
- mov pc, lr
-
-.section .mmutable, "a"
-mmutable:
- .align 14
- /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
- .set __base, 0
- .rept 0xfff
- .word (__base << 20) | 0xc12
- .set __base, __base + 1
- .endr
-
- /* 0xfff00000 : 1:1, cached mapping */
- .word (0xfff << 20) | 0x1c1e
-#endif /* CONFIG_CPU_PXA25X */
+#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8a31421..85346c5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1154,11 +1154,17 @@
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
+dtb-$(CONFIG_BCM47622) += \
+ bcm947622.dtb
+
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+dtb-$(CONFIG_STM32MP13x) += \
+ stm32mp135f-dk.dtb
+
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
@@ -1196,6 +1202,9 @@
k3-am642-sk.dtb \
k3-am642-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
+ k3-am625-r5-sk.dtb
+
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi
new file mode 100644
index 0000000..c016e12
--- /dev/null
+++ b/arch/arm/dts/bcm47622.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm47622", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ CA7_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>, <&CA7_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ cpu_off = <1>;
+ cpu_on = <2>;
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x818000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm947622.dts b/arch/arm/dts/bcm947622.dts
new file mode 100644
index 0000000..6f08372
--- /dev/null
+++ b/arch/arm/dts/bcm947622.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm47622.dtsi"
+
+/ {
+ model = "Broadcom BCM947622 Reference Board";
+ compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 1cdcc99..796d72f 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -34,6 +34,13 @@
#size-cells = <2>;
ranges;
+ sfp: efuse@1e80000 {
+ compatible = "fsl,ls1021a-sfp";
+ reg = <0x0 0x1e80000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>;
+ clock-names = "sfp";
+ };
+
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 72877d2..4960973 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -38,6 +38,13 @@
#size-cells = <2>;
ranges;
+ sfp: efuse@1e80000 {
+ compatible = "fsl,ls1021a-sfp";
+ reg = <0x0 0x1e80000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>;
+ clock-names = "sfp";
+ };
+
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index c655e00..060dc39 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -38,6 +38,13 @@
#size-cells = <2>;
ranges;
+ sfp: efuse@1e80000 {
+ compatible = "fsl,ls1021a-sfp";
+ reg = <0x0 0x1e80000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>;
+ clock-names = "sfp";
+ };
+
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1046a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
index e33e10a..c94b4ff 100644
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@@ -73,6 +73,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&uart2 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
index 433b02c..a7044b6 100644
--- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
@@ -84,6 +84,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&uart3 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
index 22d18e6..6882513 100644
--- a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
@@ -126,3 +126,7 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
index c61c6de..68978a0 100644
--- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 69fd69c..eb1dd8d 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -132,6 +132,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 4f23da3..3581955 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -110,6 +110,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&binman {
u-boot-spl-ddr {
align = <4>;
diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
index 2848b24..4419967 100644
--- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
@@ -89,6 +89,14 @@
u-boot,dm-spl;
};
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&pinctrl_i2c1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
index 37f3edc..96b9fa8 100644
--- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
@@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am62-ddr.dtsi b/arch/arm/dts/k3-am62-ddr.dtsi
new file mode 100644
index 0000000..0a8ced8
--- /dev/null
+++ b/arch/arm/dts/k3-am62-ddr.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am64-ddr.dtsi"
+&memorycontroller {
+ power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
+ <&k3_pds 55 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 170 0>, <&k3_clks 16 4>;
+};
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
new file mode 100644
index 0000000..4b6ba98
--- /dev/null
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ oc_sram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70000000 0x00 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x70000000 0x10000>;
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01880000 0x00 0xc0000>, /* GICR */
+ <0x00 0x01880000 0x00 0xc0000>, /* GICR */
+ <0x01 0x00000000 0x00 0x2000>, /* GICC */
+ <0x01 0x00010000 0x00 0x1000>, /* GICH */
+ <0x01 0x00020000 0x00 0x2000>; /* GICV */
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_conf: syscon@100000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x00100000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x00100000 0x20000>;
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+ };
+
+ dmss: bus@48000000 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
+
+ ti,sci-dev-id = <25>;
+
+ secure_proxy_main: mailbox@4d000000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d000000 0x00 0x80000>,
+ <0x00 0x4a600000 0x00 0x80000>,
+ <0x00 0x4a400000 0x00 0x80000>;
+ interrupt-names = "rx_012";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <4 68 36>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>; /* SAUL_TX_1_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>; /* RING_SAUL_TX_1_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>; /* SAUL_RX_3_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+ };
+ };
+
+ dmsc: system-controller@44043000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x00 0x44043000 0x00 0xfe0>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ main_pmx0: pinctrl@f4000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0xf4000 0x00 0x2ac>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 154 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 155 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>;
+ clock-names = "fclk";
+ };
+
+ main_i2c0: i2c@20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c1: i2c@20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20010000 0x00 0x100>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c2: i2c@20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x00 0x100>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 104 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c3: i2c@20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x00 0x100>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 2>;
+ clock-names = "fck";
+ };
+
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 172 0>;
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 173 0>;
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 174 0>;
+ };
+
+ main_gpio_intr: interrupt-controller@a00000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x00a00000 0x00 0x800>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <3>;
+ ti,interrupt-ranges = <0 32 16>;
+ };
+
+ main_gpio0: gpio@600000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00600000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <190>, <191>, <192>,
+ <193>, <194>, <195>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <87>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 77 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio1: gpio@601000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x0 0x00601000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <180>, <181>, <182>,
+ <183>, <184>, <185>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <88>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 78 0>;
+ clock-names = "gpio";
+ };
+
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 57 6>;
+ assigned-clock-parents = <&k3_clks 57 8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ ti,trm-icp = <0x2>;
+ bus-width = <8>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x9>;
+ ti,otap-del-sel-hs200 = <0x6>;
+ };
+
+ sdhci1: mmc@fa00000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,clkbuf-sel = <0x7>;
+ bus-width = <4>;
+ };
+
+ sdhci2: mmc@fa20000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,clkbuf-sel = <0x7>;
+ };
+
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x0fc00000 0x00 0x70000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 75 7>;
+ assigned-clocks = <&k3_clks 75 7>;
+ assigned-clock-parents = <&k3_clks 75 8>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0x08000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 3>;
+ assigned-clock-parents = <&k3_clks 13 11>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&wkup_conf 0x200>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 13 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ hwspinlock: spinlock@2a000000 {
+ compatible = "ti,am64-hwspinlock";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@29000000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29000000 0x00 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+};
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
new file mode 100644
index 0000000..d103824
--- /dev/null
+++ b/arch/arm/dts/k3-am62-mcu.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_pmx0: pinctrl@4084000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x04084000 0x00 0x88>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ mcu_uart0: serial@4a00000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a00000 0x00 0x100>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_i2c0: i2c@4900000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04900000 0x00 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 106 2>;
+ clock-names = "fck";
+ };
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ };
+};
diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi
new file mode 100644
index 0000000..4090134
--- /dev/null
+++ b/arch/arm/dts/k3-am62-wakeup.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_wakeup {
+ wkup_conf: syscon@43000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x43000000 0x20000>;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ };
+ };
+
+ wkup_uart0: serial@2b300000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x2b300000 0x00 0x100>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "fclk";
+ };
+
+ wkup_i2c0: i2c@2b200000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02b200000 0x00 0x100>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 4>;
+ clock-names = "fck";
+ };
+};
diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
new file mode 100644
index 0000000..bc2997b
--- /dev/null
+++ b/arch/arm/dts/k3-am62.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM62 SoC Family
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 AM625 SoC";
+ compatible = "ti,am625";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@f0000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
+ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
+ <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
+ <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
+ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
+ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
+ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+ /* MCU Domain Range */
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
+
+ /* Wakeup Domain Range */
+ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
+
+ cbass_mcu: bus@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
+ };
+
+ cbass_wakeup: bus@2b000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am62-main.dtsi"
+#include "k3-am62-mcu.dtsi"
+#include "k3-am62-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
new file mode 100644
index 0000000..2691af4
--- /dev/null
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM625 SK dts file for R5 SPL
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am625-sk.dts"
+#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am625-sk-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ serial0 = &wkup_uart0;
+ serial3 = &main_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ u-boot,dm-spl;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&cbass_main {
+ sa3_secproxy: secproxy@44880000 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "rt", "scfg", "target_data";
+ reg = <0x00 0x44880000 0x00 0x20000>,
+ <0x0 0x44860000 0x0 0x20000>,
+ <0x0 0x43600000 0x0 0x10000>;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ u-boot,dm-spl;
+ };
+};
+
+&mcu_pmx0 {
+ u-boot,dm-spl;
+ wkup_uart0_pins_default: wkup-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
+ AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
+ AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
+ AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main_uart1_pins_default: main-uart1-pins-default {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
+ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
+ AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
+ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ status = "okay";
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
new file mode 100644
index 0000000..e1971ec
--- /dev/null
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common AM625 SK dts file for SPLs
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ mmc1 = &sdhci1;
+ };
+};
+
+&cbass_main{
+ u-boot,dm-spl;
+
+ timer1: timer@2400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x00 0x2400000 0x00 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&dmss {
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&wkup_conf {
+ u-boot,dm-spl;
+};
+
+&chipid {
+ u-boot,dm-spl;
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_uart0 {
+ u-boot,dm-spl;
+};
+
+&main_uart0_pins_default {
+ u-boot,dm-spl;
+};
+
+&main_uart1 {
+ u-boot,dm-spl;
+};
+
+&cbass_mcu {
+ u-boot,dm-spl;
+};
+
+&cbass_wakeup {
+ u-boot,dm-spl;
+};
+
+&mcu_pmx0 {
+ u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+};
+
+&sdhci1 {
+ u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
new file mode 100644
index 0000000..76b06ea
--- /dev/null
+++ b/arch/arm/dts/k3-am625-sk.dts
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM625 SK: https://www.ti.com/lit/zip/sprr448
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am625.dtsi"
+
+/ {
+ compatible = "ti,am625-sk", "ti,am625";
+ model = "Texas Instruments AM625 SK";
+
+ aliases {
+ serial2 = &main_uart0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9db00000 0x00 0xc00000>;
+ no-map;
+ };
+ };
+};
+
+&main_pmx0 {
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
+ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
+ AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
+ AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
+ AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
+ AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
+ AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* WKUP UART0 is used by DM firmware */
+ status = "reserved";
+};
+
+&mcu_uart0 {
+ status = "disabled";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&main_uart1 {
+ /* Main UART1 is used by TIFS firmware */
+ status = "reserved";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&mcu_i2c0 {
+ status = "disabled";
+};
+
+&wkup_i2c0 {
+ status = "disabled";
+};
+
+&main_i2c0 {
+ status = "disabled";
+};
+
+&main_i2c1 {
+ status = "disabled";
+};
+
+&main_i2c2 {
+ status = "disabled";
+};
+
+&main_i2c3 {
+ status = "disabled";
+};
+
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi
new file mode 100644
index 0000000..887f31c
--- /dev/null
+++ b/arch/arm/dts/k3-am625.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC family in Quad core configuration
+ *
+ * TRM: https://www.ti.com/lit/pdf/spruiv7
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am62.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+};
diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
new file mode 100644
index 0000000..d92e3ce
--- /dev/null
+++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
@@ -0,0 +1,2189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated with the
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60
+ * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time)
+ * DDR Type: DDR4
+ * Frequency = 800MHz (1600MTs)
+ * Density: 16Gb
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000A00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x000890B8
+#define DDRSS_CTL_8_DATA 0x00000000
+#define DDRSS_CTL_9_DATA 0x00000000
+#define DDRSS_CTL_10_DATA 0x00000000
+#define DDRSS_CTL_11_DATA 0x000890B8
+#define DDRSS_CTL_12_DATA 0x00000000
+#define DDRSS_CTL_13_DATA 0x00000000
+#define DDRSS_CTL_14_DATA 0x00000000
+#define DDRSS_CTL_15_DATA 0x000890B8
+#define DDRSS_CTL_16_DATA 0x00000000
+#define DDRSS_CTL_17_DATA 0x00000000
+#define DDRSS_CTL_18_DATA 0x00000000
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01000100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x00027100
+#define DDRSS_CTL_24_DATA 0x00061A80
+#define DDRSS_CTL_25_DATA 0x02550255
+#define DDRSS_CTL_26_DATA 0x00000255
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00000000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x00000000
+#define DDRSS_CTL_35_DATA 0x00000000
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0400091C
+#define DDRSS_CTL_39_DATA 0x1C1C1C1C
+#define DDRSS_CTL_40_DATA 0x0400091C
+#define DDRSS_CTL_41_DATA 0x1C1C1C1C
+#define DDRSS_CTL_42_DATA 0x0400091C
+#define DDRSS_CTL_43_DATA 0x1C1C1C1C
+#define DDRSS_CTL_44_DATA 0x05050404
+#define DDRSS_CTL_45_DATA 0x00002706
+#define DDRSS_CTL_46_DATA 0x0602001D
+#define DDRSS_CTL_47_DATA 0x05001D0B
+#define DDRSS_CTL_48_DATA 0x00270605
+#define DDRSS_CTL_49_DATA 0x0602001D
+#define DDRSS_CTL_50_DATA 0x05001D0B
+#define DDRSS_CTL_51_DATA 0x00270605
+#define DDRSS_CTL_52_DATA 0x0602001D
+#define DDRSS_CTL_53_DATA 0x07001D0B
+#define DDRSS_CTL_54_DATA 0x00180807
+#define DDRSS_CTL_55_DATA 0x0400DB60
+#define DDRSS_CTL_56_DATA 0x07070009
+#define DDRSS_CTL_57_DATA 0x00001808
+#define DDRSS_CTL_58_DATA 0x0400DB60
+#define DDRSS_CTL_59_DATA 0x07070009
+#define DDRSS_CTL_60_DATA 0x00001808
+#define DDRSS_CTL_61_DATA 0x0400DB60
+#define DDRSS_CTL_62_DATA 0x03000009
+#define DDRSS_CTL_63_DATA 0x0D0C0002
+#define DDRSS_CTL_64_DATA 0x0D0C0D0C
+#define DDRSS_CTL_65_DATA 0x01010000
+#define DDRSS_CTL_66_DATA 0x03191919
+#define DDRSS_CTL_67_DATA 0x0B0B0B0B
+#define DDRSS_CTL_68_DATA 0x00000B0B
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x01180803
+#define DDRSS_CTL_73_DATA 0x00001860
+#define DDRSS_CTL_74_DATA 0x00000118
+#define DDRSS_CTL_75_DATA 0x00001860
+#define DDRSS_CTL_76_DATA 0x00000118
+#define DDRSS_CTL_77_DATA 0x00001860
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x00000000
+#define DDRSS_CTL_80_DATA 0x00000000
+#define DDRSS_CTL_81_DATA 0x00000000
+#define DDRSS_CTL_82_DATA 0x00000000
+#define DDRSS_CTL_83_DATA 0x00000000
+#define DDRSS_CTL_84_DATA 0x00000000
+#define DDRSS_CTL_85_DATA 0x00000000
+#define DDRSS_CTL_86_DATA 0x00000000
+#define DDRSS_CTL_87_DATA 0x00090009
+#define DDRSS_CTL_88_DATA 0x00000009
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x00000000
+#define DDRSS_CTL_93_DATA 0x00000000
+#define DDRSS_CTL_94_DATA 0x00010001
+#define DDRSS_CTL_95_DATA 0x00025501
+#define DDRSS_CTL_96_DATA 0x02550120
+#define DDRSS_CTL_97_DATA 0x02550120
+#define DDRSS_CTL_98_DATA 0x01200120
+#define DDRSS_CTL_99_DATA 0x01200120
+#define DDRSS_CTL_100_DATA 0x00000000
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00000000
+#define DDRSS_CTL_103_DATA 0x00000000
+#define DDRSS_CTL_104_DATA 0x00000000
+#define DDRSS_CTL_105_DATA 0x00000000
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00061800
+#define DDRSS_CTL_120_DATA 0x00061800
+#define DDRSS_CTL_121_DATA 0x00061800
+#define DDRSS_CTL_122_DATA 0x00061800
+#define DDRSS_CTL_123_DATA 0x00061800
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000AAA0
+#define DDRSS_CTL_126_DATA 0x00061800
+#define DDRSS_CTL_127_DATA 0x00061800
+#define DDRSS_CTL_128_DATA 0x00061800
+#define DDRSS_CTL_129_DATA 0x00061800
+#define DDRSS_CTL_130_DATA 0x00061800
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x0000AAA0
+#define DDRSS_CTL_133_DATA 0x00061800
+#define DDRSS_CTL_134_DATA 0x00061800
+#define DDRSS_CTL_135_DATA 0x00061800
+#define DDRSS_CTL_136_DATA 0x00061800
+#define DDRSS_CTL_137_DATA 0x00061800
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x0000AAA0
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x080C0000
+#define DDRSS_CTL_157_DATA 0x080C080C
+#define DDRSS_CTL_158_DATA 0x08000000
+#define DDRSS_CTL_159_DATA 0x00000808
+#define DDRSS_CTL_160_DATA 0x000E0000
+#define DDRSS_CTL_161_DATA 0x00080808
+#define DDRSS_CTL_162_DATA 0x0E000000
+#define DDRSS_CTL_163_DATA 0x08080800
+#define DDRSS_CTL_164_DATA 0x00000000
+#define DDRSS_CTL_165_DATA 0x0000080E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000000
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x00000000
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00042400
+#define DDRSS_CTL_205_DATA 0x00000301
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000424
+#define DDRSS_CTL_208_DATA 0x00000301
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000424
+#define DDRSS_CTL_211_DATA 0x00000301
+#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_213_DATA 0x00000424
+#define DDRSS_CTL_214_DATA 0x00000301
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000424
+#define DDRSS_CTL_217_DATA 0x00000301
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000424
+#define DDRSS_CTL_220_DATA 0x00000301
+#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000000
+#define DDRSS_CTL_228_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0x00000000
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00001401
+#define DDRSS_CTL_237_DATA 0x00001401
+#define DDRSS_CTL_238_DATA 0x00001401
+#define DDRSS_CTL_239_DATA 0x00001401
+#define DDRSS_CTL_240_DATA 0x00001401
+#define DDRSS_CTL_241_DATA 0x00001401
+#define DDRSS_CTL_242_DATA 0x00000493
+#define DDRSS_CTL_243_DATA 0x00000493
+#define DDRSS_CTL_244_DATA 0x00000493
+#define DDRSS_CTL_245_DATA 0x00000493
+#define DDRSS_CTL_246_DATA 0x00000493
+#define DDRSS_CTL_247_DATA 0x00000493
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x00000000
+#define DDRSS_CTL_258_DATA 0x00000000
+#define DDRSS_CTL_259_DATA 0x00000000
+#define DDRSS_CTL_260_DATA 0x00000000
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x00000000
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x00000000
+#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_268_DATA 0x00000000
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_271_DATA 0x00000000
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000000
+#define DDRSS_CTL_275_DATA 0x00000000
+#define DDRSS_CTL_276_DATA 0x00000000
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00040000
+#define DDRSS_CTL_306_DATA 0x00800200
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x02000400
+#define DDRSS_CTL_309_DATA 0x00000080
+#define DDRSS_CTL_310_DATA 0x00040000
+#define DDRSS_CTL_311_DATA 0x00800200
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x00000000
+#define DDRSS_CTL_314_DATA 0x00000000
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_322_DATA 0x0A000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x00000000
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x00000000
+#define DDRSS_CTL_331_DATA 0x01000000
+#define DDRSS_CTL_332_DATA 0x00000100
+#define DDRSS_CTL_333_DATA 0x00010000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x0C000000
+#define DDRSS_CTL_371_DATA 0x060C0606
+#define DDRSS_CTL_372_DATA 0x06060C06
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x02000000
+#define DDRSS_CTL_375_DATA 0x05020101
+#define DDRSS_CTL_376_DATA 0x00000505
+#define DDRSS_CTL_377_DATA 0x02020200
+#define DDRSS_CTL_378_DATA 0x02020202
+#define DDRSS_CTL_379_DATA 0x02020202
+#define DDRSS_CTL_380_DATA 0x02020202
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x04000100
+#define DDRSS_CTL_384_DATA 0x1E000004
+#define DDRSS_CTL_385_DATA 0x000030C0
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x0000DB60
+#define DDRSS_CTL_391_DATA 0x0001E780
+#define DDRSS_CTL_392_DATA 0x0C0D0302
+#define DDRSS_CTL_393_DATA 0x001E090A
+#define DDRSS_CTL_394_DATA 0x000030C0
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x0000DB60
+#define DDRSS_CTL_400_DATA 0x0001E780
+#define DDRSS_CTL_401_DATA 0x0C0D0302
+#define DDRSS_CTL_402_DATA 0x001E090A
+#define DDRSS_CTL_403_DATA 0x000030C0
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x0000DB60
+#define DDRSS_CTL_409_DATA 0x0001E780
+#define DDRSS_CTL_410_DATA 0x0C0D0302
+#define DDRSS_CTL_411_DATA 0x0000090A
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x00000000
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000A00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000000
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x00000000
+#define DDRSS_PI_15_DATA 0x00010001
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x280D0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x00060602
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x00000055
+#define DDRSS_PI_36_DATA 0x000000AA
+#define DDRSS_PI_37_DATA 0x000000AD
+#define DDRSS_PI_38_DATA 0x00000052
+#define DDRSS_PI_39_DATA 0x0000006A
+#define DDRSS_PI_40_DATA 0x00000095
+#define DDRSS_PI_41_DATA 0x00000095
+#define DDRSS_PI_42_DATA 0x000000AD
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x00000000
+#define DDRSS_PI_55_DATA 0x00010000
+#define DDRSS_PI_56_DATA 0x00000000
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x00001400
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x01000000
+#define DDRSS_PI_63_DATA 0x00000404
+#define DDRSS_PI_64_DATA 0x00000001
+#define DDRSS_PI_65_DATA 0x0001010E
+#define DDRSS_PI_66_DATA 0x02040100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000005
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x04000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000300
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010100
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00027100
+#define DDRSS_PI_137_DATA 0x00061A80
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00007800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00141414
+#define DDRSS_PI_167_DATA 0x0000003A
+#define DDRSS_PI_168_DATA 0x0000003A
+#define DDRSS_PI_169_DATA 0x0004003A
+#define DDRSS_PI_170_DATA 0x04000400
+#define DDRSS_PI_171_DATA 0xC8040009
+#define DDRSS_PI_172_DATA 0x0400091C
+#define DDRSS_PI_173_DATA 0x00091CC8
+#define DDRSS_PI_174_DATA 0x001CC804
+#define DDRSS_PI_175_DATA 0x00000118
+#define DDRSS_PI_176_DATA 0x00001860
+#define DDRSS_PI_177_DATA 0x00000118
+#define DDRSS_PI_178_DATA 0x00001860
+#define DDRSS_PI_179_DATA 0x00000118
+#define DDRSS_PI_180_DATA 0x04001860
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001901
+#define DDRSS_PI_183_DATA 0x00190019
+#define DDRSS_PI_184_DATA 0x010C010C
+#define DDRSS_PI_185_DATA 0x0000010C
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05000000
+#define DDRSS_PI_188_DATA 0x01010505
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x00181818
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x0D000000
+#define DDRSS_PI_194_DATA 0x0A0A0D0D
+#define DDRSS_PI_195_DATA 0x0303030A
+#define DDRSS_PI_196_DATA 0x00000000
+#define DDRSS_PI_197_DATA 0x00000000
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x00000000
+#define DDRSS_PI_200_DATA 0x00000000
+#define DDRSS_PI_201_DATA 0x00000000
+#define DDRSS_PI_202_DATA 0x00000000
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x00000000
+#define DDRSS_PI_206_DATA 0x00000000
+#define DDRSS_PI_207_DATA 0x00000000
+#define DDRSS_PI_208_DATA 0x00000000
+#define DDRSS_PI_209_DATA 0x0D090000
+#define DDRSS_PI_210_DATA 0x0D09000D
+#define DDRSS_PI_211_DATA 0x0D09000D
+#define DDRSS_PI_212_DATA 0x0000000D
+#define DDRSS_PI_213_DATA 0x00000000
+#define DDRSS_PI_214_DATA 0x00000000
+#define DDRSS_PI_215_DATA 0x00000000
+#define DDRSS_PI_216_DATA 0x00000000
+#define DDRSS_PI_217_DATA 0x16000000
+#define DDRSS_PI_218_DATA 0x001600C8
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x010100C8
+#define DDRSS_PI_221_DATA 0x00001B01
+#define DDRSS_PI_222_DATA 0x1F0F0053
+#define DDRSS_PI_223_DATA 0x05000001
+#define DDRSS_PI_224_DATA 0x001B0A0D
+#define DDRSS_PI_225_DATA 0x1F0F0053
+#define DDRSS_PI_226_DATA 0x05000001
+#define DDRSS_PI_227_DATA 0x001B0A0D
+#define DDRSS_PI_228_DATA 0x1F0F0053
+#define DDRSS_PI_229_DATA 0x05000001
+#define DDRSS_PI_230_DATA 0x00010A0D
+#define DDRSS_PI_231_DATA 0x0C0B0700
+#define DDRSS_PI_232_DATA 0x000D0605
+#define DDRSS_PI_233_DATA 0x0000C570
+#define DDRSS_PI_234_DATA 0x0000001D
+#define DDRSS_PI_235_DATA 0x180A0800
+#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_237_DATA 0x0D06050C
+#define DDRSS_PI_238_DATA 0x0000C570
+#define DDRSS_PI_239_DATA 0x0000001D
+#define DDRSS_PI_240_DATA 0x180A0800
+#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_242_DATA 0x0D06050C
+#define DDRSS_PI_243_DATA 0x0000C570
+#define DDRSS_PI_244_DATA 0x0000001D
+#define DDRSS_PI_245_DATA 0x180A0800
+#define DDRSS_PI_246_DATA 0x00001C1C
+#define DDRSS_PI_247_DATA 0x000030C0
+#define DDRSS_PI_248_DATA 0x0001E780
+#define DDRSS_PI_249_DATA 0x000030C0
+#define DDRSS_PI_250_DATA 0x0001E780
+#define DDRSS_PI_251_DATA 0x000030C0
+#define DDRSS_PI_252_DATA 0x0001E780
+#define DDRSS_PI_253_DATA 0x02550255
+#define DDRSS_PI_254_DATA 0x03030255
+#define DDRSS_PI_255_DATA 0x00025503
+#define DDRSS_PI_256_DATA 0x02550255
+#define DDRSS_PI_257_DATA 0x0C080C08
+#define DDRSS_PI_258_DATA 0x00000C08
+#define DDRSS_PI_259_DATA 0x000890B8
+#define DDRSS_PI_260_DATA 0x00000000
+#define DDRSS_PI_261_DATA 0x00000000
+#define DDRSS_PI_262_DATA 0x00000000
+#define DDRSS_PI_263_DATA 0x00000120
+#define DDRSS_PI_264_DATA 0x000890B8
+#define DDRSS_PI_265_DATA 0x00000000
+#define DDRSS_PI_266_DATA 0x00000000
+#define DDRSS_PI_267_DATA 0x00000000
+#define DDRSS_PI_268_DATA 0x00000120
+#define DDRSS_PI_269_DATA 0x000890B8
+#define DDRSS_PI_270_DATA 0x00000000
+#define DDRSS_PI_271_DATA 0x00000000
+#define DDRSS_PI_272_DATA 0x00000000
+#define DDRSS_PI_273_DATA 0x02000120
+#define DDRSS_PI_274_DATA 0x00000080
+#define DDRSS_PI_275_DATA 0x00020000
+#define DDRSS_PI_276_DATA 0x00000080
+#define DDRSS_PI_277_DATA 0x00020000
+#define DDRSS_PI_278_DATA 0x00000080
+#define DDRSS_PI_279_DATA 0x00000000
+#define DDRSS_PI_280_DATA 0x00000000
+#define DDRSS_PI_281_DATA 0x00040404
+#define DDRSS_PI_282_DATA 0x00000000
+#define DDRSS_PI_283_DATA 0x02010102
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000202
+#define DDRSS_PI_286_DATA 0x00000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x00000000
+#define DDRSS_PI_289_DATA 0x00000000
+#define DDRSS_PI_290_DATA 0x00000000
+#define DDRSS_PI_291_DATA 0x0D100F00
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000424
+#define DDRSS_PI_298_DATA 0x00000301
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000000
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00001401
+#define DDRSS_PI_303_DATA 0x00000493
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000424
+#define DDRSS_PI_306_DATA 0x00000301
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x00000000
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00001401
+#define DDRSS_PI_311_DATA 0x00000493
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x00000424
+#define DDRSS_PI_314_DATA 0x00000301
+#define DDRSS_PI_315_DATA 0x00000000
+#define DDRSS_PI_316_DATA 0x00000000
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00001401
+#define DDRSS_PI_319_DATA 0x00000493
+#define DDRSS_PI_320_DATA 0x00000000
+#define DDRSS_PI_321_DATA 0x00000424
+#define DDRSS_PI_322_DATA 0x00000301
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000000
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00001401
+#define DDRSS_PI_327_DATA 0x00000493
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000424
+#define DDRSS_PI_330_DATA 0x00000301
+#define DDRSS_PI_331_DATA 0x00000000
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00001401
+#define DDRSS_PI_335_DATA 0x00000493
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x00000424
+#define DDRSS_PI_338_DATA 0x00000301
+#define DDRSS_PI_339_DATA 0x00000000
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00001401
+#define DDRSS_PI_343_DATA 0x00000493
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PHY_0_DATA 0x04C00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00000200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x00000000
+#define DDRSS_PHY_6_DATA 0x00000000
+#define DDRSS_PHY_7_DATA 0x00000000
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x010101FF
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00004
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660201
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00070820
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CCB001
+#define DDRSS_PHY_75_DATA 0x2000CCB0
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x10100303
+#define DDRSS_PHY_80_DATA 0x10101010
+#define DDRSS_PHY_81_DATA 0x10101010
+#define DDRSS_PHY_82_DATA 0x00021010
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51515041
+#define DDRSS_PHY_89_DATA 0x31804000
+#define DDRSS_PHY_90_DATA 0x04BF0340
+#define DDRSS_PHY_91_DATA 0x01008080
+#define DDRSS_PHY_92_DATA 0x04050001
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C14
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x02800280
+#define DDRSS_PHY_106_DATA 0x02800280
+#define DDRSS_PHY_107_DATA 0x02800280
+#define DDRSS_PHY_108_DATA 0x02800280
+#define DDRSS_PHY_109_DATA 0x00000280
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01000080
+#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x00000000
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04C00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00000200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x00000000
+#define DDRSS_PHY_262_DATA 0x00000000
+#define DDRSS_PHY_263_DATA 0x00000000
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x010101FF
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00004
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660201
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00070820
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CCB001
+#define DDRSS_PHY_331_DATA 0x2000CCB0
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x10100303
+#define DDRSS_PHY_336_DATA 0x10101010
+#define DDRSS_PHY_337_DATA 0x10101010
+#define DDRSS_PHY_338_DATA 0x00021010
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51515041
+#define DDRSS_PHY_345_DATA 0x31804000
+#define DDRSS_PHY_346_DATA 0x04BF0340
+#define DDRSS_PHY_347_DATA 0x01008080
+#define DDRSS_PHY_348_DATA 0x04050001
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C14
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x02800280
+#define DDRSS_PHY_362_DATA 0x02800280
+#define DDRSS_PHY_363_DATA 0x02800280
+#define DDRSS_PHY_364_DATA 0x02800280
+#define DDRSS_PHY_365_DATA 0x00000280
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01000080
+#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x00000000
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000100
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000000
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x00000000
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x00000000
+#define DDRSS_PHY_527_DATA 0x00000000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x00000000
+#define DDRSS_PHY_533_DATA 0x00000000
+#define DDRSS_PHY_534_DATA 0x00000000
+#define DDRSS_PHY_535_DATA 0x00000000
+#define DDRSS_PHY_536_DATA 0x00000000
+#define DDRSS_PHY_537_DATA 0x00000000
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x103F0000
+#define DDRSS_PHY_542_DATA 0x000F0100
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000003E
+#define DDRSS_PHY_553_DATA 0x00000000
+#define DDRSS_PHY_554_DATA 0x00000000
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000100
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000000
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x00000000
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x00000000
+#define DDRSS_PHY_783_DATA 0x00000000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x00000000
+#define DDRSS_PHY_789_DATA 0x00000000
+#define DDRSS_PHY_790_DATA 0x00000000
+#define DDRSS_PHY_791_DATA 0x00000000
+#define DDRSS_PHY_792_DATA 0x00000000
+#define DDRSS_PHY_793_DATA 0x00000000
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x16A4A0E6
+#define DDRSS_PHY_797_DATA 0x103F0000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000003E
+#define DDRSS_PHY_809_DATA 0x00000000
+#define DDRSS_PHY_810_DATA 0x00000000
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000100
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000000
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00000000
+#define DDRSS_PHY_1036_DATA 0x00000000
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x00000000
+#define DDRSS_PHY_1039_DATA 0x00000000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x00000000
+#define DDRSS_PHY_1046_DATA 0x00000000
+#define DDRSS_PHY_1047_DATA 0x00000000
+#define DDRSS_PHY_1048_DATA 0x00000000
+#define DDRSS_PHY_1049_DATA 0x00000000
+#define DDRSS_PHY_1050_DATA 0x00000000
+#define DDRSS_PHY_1051_DATA 0x00000000
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10030000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000003E
+#define DDRSS_PHY_1065_DATA 0x00000000
+#define DDRSS_PHY_1066_DATA 0x00000000
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000100
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x01002000
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x00010100
+#define DDRSS_PHY_1297_DATA 0x00000001
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00040000
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07070001
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000046
+#define DDRSS_PHY_1334_DATA 0x00000400
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00000098
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000100
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020400
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03900390
+#define DDRSS_PHY_1382_DATA 0x03900390
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x31823FC7
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000D3F
+#define DDRSS_PHY_1390_DATA 0x30000D3F
+#define DDRSS_PHY_1391_DATA 0x300D3F11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x000D3FCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x300D3F11
+#define DDRSS_PHY_1396_DATA 0x01990000
+#define DDRSS_PHY_1397_DATA 0x300C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x300C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x300D3F11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x300D3F11
+#define DDRSS_PHY_1404_DATA 0x01990000
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
index 26567f4..1d0659e 100644
--- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
@@ -198,7 +198,7 @@
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "host";
+ dr_mode = "peripheral";
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 24881c8..455698a 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -309,6 +309,7 @@
&dwc3_0 {
status = "okay";
u-boot,dm-spl;
+ /delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 677a72d..b2b81f8 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -192,6 +192,22 @@
u-boot,dm-spl;
};
+&hbmc {
+ u-boot,dm-spl;
+
+ flash@0,0 {
+ u-boot,dm-spl;
+ };
+};
+
+&hbmc_mux {
+ u-boot,dm-spl;
+};
+
+&wkup_gpio0 {
+ u-boot,dm-spl;
+};
+
&ospi0 {
u-boot,dm-spl;
@@ -208,6 +224,14 @@
};
};
+&mcu_fss0_hpb0_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_gpio_pins_default {
+ u-boot,dm-spl;
+};
+
&mcu_fss0_ospi1_pins_default {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index f3b6302..1b60054 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -213,6 +213,12 @@
>;
};
+ wkup_gpio_pins_default: wkup-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+ >;
+ };
+
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
@@ -381,6 +387,11 @@
phy-names = "cdns3,usb3-phy";
};
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
&usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>;
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index d2dceda..22166c7 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -170,12 +170,30 @@
};
fss: fss@47000000 {
- compatible = "simple-bus";
+ compatible = "syscon", "simple-mfd";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ hbmc_mux: hbmc-mux {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4 0x2>; /* HBMC select */
+ };
+
+ hbmc: hyperbus@47034000 {
+ compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
+ reg = <0x0 0x47034000 0x0 0x100>,
+ <0x5 0x00000000 0x1 0x0000000>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ mux-controls = <&hbmc_mux 0>;
+ assigned-clocks = <&k3_clks 102 0>;
+ assigned-clock-rates = <250000000>;
+ };
+
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index a14b148..ab9d6e6 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -129,6 +129,31 @@
>;
};
+ mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+ J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+ J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+ >;
+ };
+
+ wkup_gpio_pins_default: wkup-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
+ >;
+ };
+
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@@ -207,6 +232,11 @@
status = "okay";
};
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
&mcu_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
@@ -307,6 +337,21 @@
};
};
+&hbmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+ ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
+ <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
+
+ flash@0,0 {
+ compatible = "cypress,hyperflash", "cfi-flash";
+ reg = <0x0 0x0 0x4000000>;
+ };
+};
+
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi
index 2fee290..a725435 100644
--- a/arch/arm/dts/k3-j721e-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721e-som-p0.dtsi
@@ -150,6 +150,25 @@
>;
};
+ mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+ J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+ J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+ >;
+ };
+
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@@ -167,6 +186,19 @@
};
};
+&hbmc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+ ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
+ <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
+
+ flash@0,0 {
+ compatible = "cypress,hyperflash", "cfi-flash";
+ reg = <0x0 0x0 0x4000000>;
+ };
+};
+
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index be330c1..4f65ee7 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -31,17 +31,24 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
- clocks = <&cluster1_clk>;
+ clocks = <&clockgen 1 0>;
};
cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
- clocks = <&cluster1_clk>;
+ clocks = <&clockgen 1 0>;
};
};
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@@ -82,6 +89,13 @@
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
};
+ sfp: efuse@1e80000 {
+ compatible = "fsl,ls1021a-sfp";
+ reg = <0x0 0x1e80000 0x0 0x10000>;
+ clocks = <&clockgen 4 3>;
+ clock-names = "sfp";
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg", "syscon";
reg = <0x1ee0000 0x10000>;
@@ -185,41 +199,10 @@
};
clockgen: clocking@1ee1000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1ee1000 0x10000>;
-
- sysclk: sysclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-output-names = "sysclk";
- };
-
- cga_pll1: pll@800 {
- compatible = "fsl,qoriq-core-pll-2.0";
- #clock-cells = <1>;
- reg = <0x800 0x10>;
- clocks = <&sysclk>;
- clock-output-names = "cga-pll1", "cga-pll1-div2",
- "cga-pll1-div4";
- };
-
- platform_clk: pll@c00 {
- compatible = "fsl,qoriq-core-pll-2.0";
- #clock-cells = <1>;
- reg = <0xc00 0x10>;
- clocks = <&sysclk>;
- clock-output-names = "platform-clk", "platform-clk-div2";
- };
-
- cluster1_clk: clk0c0@0 {
- compatible = "fsl,qoriq-core-mux-2.0";
- #clock-cells = <0>;
- reg = <0x0 0x10>;
- clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
- clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
- clock-output-names = "cluster1-clk";
- };
+ compatible = "fsl,ls1021a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
};
dspi0: dspi@2100000 {
@@ -229,7 +212,7 @@
reg = <0x2100000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -242,7 +225,7 @@
reg = <0x2110000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -265,7 +248,7 @@
reg = <0x2180000 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
status = "disabled";
};
@@ -276,7 +259,7 @@
reg = <0x2190000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
status = "disabled";
};
@@ -287,7 +270,7 @@
reg = <0x21a0000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
status = "disabled";
};
@@ -336,7 +319,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2960000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -345,7 +328,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2970000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -354,7 +337,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2980000 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -363,7 +346,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2990000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -372,7 +355,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x29a0000 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@@ -381,7 +364,7 @@
compatible = "fsl,imx21-wdt";
reg = <0x2ad0000 0x10000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "wdog-en";
big-endian;
};
@@ -390,7 +373,7 @@
compatible = "fsl,vf610-sai";
reg = <0x2b50000 0x10000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "sai";
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
@@ -403,7 +386,7 @@
compatible = "fsl,vf610-sai";
reg = <0x2b60000 0x10000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
+ clocks = <&clockgen 4 1>;
clock-names = "sai";
dma-names = "tx", "rx";
dmas = <&edma0 1 45>,
@@ -424,8 +407,8 @@
dma-channels = <32>;
big-endian;
clock-names = "dmamux0", "dmamux1";
- clocks = <&platform_clk 1>,
- <&platform_clk 1>;
+ clocks = <&clockgen 4 1>,
+ <&clockgen 4 1>;
};
enet0: ethernet@2d10000 {
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
new file mode 100644
index 0000000..d2472cd
--- /dev/null
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc1_clk_pins_a: sdmmc1-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc2_clk_pins_a: sdmmc2-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ uart4_pins_a: uart4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi
new file mode 100644
index 0000000..1b5b358
--- /dev/null
+++ b/arch/arm/dts/stm32mp13-u-boot.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ pinctrl0 = &pinctrl;
+ };
+
+ /* need PSCI for sysreset during board_f */
+ psci {
+ u-boot,dm-pre-proper;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ddr: ddr@5a003000 {
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp13-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ status = "okay";
+ };
+ };
+};
+
+&bsec {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ u-boot,dm-pre-reloc;
+};
+
+&iwdg2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&syscfg {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
new file mode 100644
index 0000000..950e172
--- /dev/null
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
+ clocks {
+ clk_axi: clk-axi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <266500000>;
+ };
+
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_pclk3: clk-pclk3 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <104438965>;
+ };
+
+ clk_pclk4: clk-pclk4 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <133250000>;
+ };
+
+ clk_pll4_p: clk-pll4_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ clk_pll4_r: clk-pll4_r {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <99000000>;
+ };
+ };
+
+ intc: interrupt-controller@a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ always-on;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_hsi>;
+ status = "disabled";
+ };
+
+ dma1: dma-controller@48000000 {
+ compatible = "st,stm32-dma";
+ reg = <0x48000000 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_pclk4>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ };
+
+ dma2: dma-controller@48001000 {
+ compatible = "st,stm32-dma";
+ reg = <0x48001000 0x400>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_pclk4>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ };
+
+ dmamux1: dma-router@48002000 {
+ compatible = "st,stm32h7-dmamux";
+ reg = <0x48002000 0x40>;
+ clocks = <&clk_pclk4>;
+ #dma-cells = <3>;
+ dma-masters = <&dma1 &dma2>;
+ dma-requests = <128>;
+ dma-channels = <16>;
+ };
+
+ exti: interrupt-controller@5000d000 {
+ compatible = "st,stm32mp13-exti", "syscon";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000d000 0x400>;
+ };
+
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ clocks = <&clk_pclk3>;
+ };
+
+ mdma: dma-controller@58000000 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x58000000 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_pclk4>;
+ #dma-cells = <5>;
+ dma-channels = <32>;
+ dma-requests = <48>;
+ };
+
+ sdmmc1: mmc@58005000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x20253180>;
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&clk_pll4_p>;
+ clock-names = "apb_pclk";
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
+ status = "disabled";
+ };
+
+ sdmmc2: mmc@58007000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x20253180>;
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&clk_pll4_p>;
+ clock-names = "apb_pclk";
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
+ status = "disabled";
+ };
+
+ iwdg2: watchdog@5a002000 {
+ compatible = "st,stm32mp1-iwdg";
+ reg = <0x5a002000 0x400>;
+ clocks = <&clk_pclk4>, <&clk_lsi>;
+ clock-names = "pclk", "lsi";
+ status = "disabled";
+ };
+
+ bsec: efuse@5c005000 {
+ compatible = "st,stm32mp13-bsec";
+ reg = <0x5c005000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ part_number_otp: part_number_otp@4 {
+ reg = <0x4 0x2>;
+ };
+ ts_cal1: calib@5c {
+ reg = <0x5c 0x2>;
+ };
+ ts_cal2: calib@5e {
+ reg = <0x5e 0x2>;
+ };
+ };
+
+ /*
+ * Break node order to solve dependency probe issue between
+ * pinctrl and exti.
+ */
+ pinctrl: pin-controller@50002000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp135-pinctrl";
+ ranges = <0 0x50002000 0x8400>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOH";
+ ngpios = <15>;
+ gpio-ranges = <&pinctrl 0 112 15>;
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&clk_pclk4>;
+ st,bank-name = "GPIOI";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 128 8>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
new file mode 100644
index 0000000..0fb1386
--- /dev/null
+++ b/arch/arm/dts/stm32mp133.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp131.dtsi"
+
+/ {
+ soc {
+ m_can1: can@4400e000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clk_hse>, <&clk_pll4_r>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+
+ m_can2: can@4400f000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clk_hse>, <&clk_pll4_r>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp135.dtsi b/arch/arm/dts/stm32mp135.dtsi
new file mode 100644
index 0000000..abf2acd
--- /dev/null
+++ b/arch/arm/dts/stm32mp135.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp133.dtsi"
+
+/ {
+ soc {
+ };
+};
diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
new file mode 100644
index 0000000..dfe5bbb
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp13-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc1;
+ };
+
+ config {
+ u-boot,mmc-env-partition = "u-boot-env";
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
new file mode 100644
index 0000000..ee100d1
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP135F-DK Discovery Board";
+ compatible = "st,stm32mp135f-dk", "st,stm32mp135";
+
+ aliases {
+ serial0 = &uart4;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ vdd_sd: vdd-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ broken-cd;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi
new file mode 100644
index 0000000..fa6889e
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xc.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp: crypto@54002000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54002000 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_axi>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi
new file mode 100644
index 0000000..fa6889e
--- /dev/null
+++ b/arch/arm/dts/stm32mp13xf.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp: crypto@54002000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54002000 0x400>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_axi>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 06adf66..61db173 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -142,25 +142,6 @@
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define TP_INIT_PER_CLUSTER 4
-/*
- * Define default values for some CCSR macros to make header files cleaner*
- *
- * To completely disable CCSR relocation in a board header file, define
- * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
- * to a value that is the same as CONFIG_SYS_CCSRBAR.
- */
-
-#ifdef CONFIG_SYS_CCSRBAR_PHYS
-#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
-CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
-#endif
-
-#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
-#endif
-
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR 0x01000000
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 863618a..304cd79 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -230,6 +230,10 @@
#define DCFG_BASE 0x01e00000
#define DCFG_PORSR1 0x000
#define DCFG_PORSR1_RCW_SRC 0xff800000
+#define DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000
+#define DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000
+#define DCFG_PORSR1_RCW_SRC_I2C 0x05000000
+#define DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
#define DCFG_RCWSR12 0x12c
#define DCFG_RCWSR12_SDHC_SHIFT 24
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f2ba182..b0acf67 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -42,24 +42,6 @@
#define DCFG_DCSR_PORCR1 0
-/*
- * Define default values for some CCSR macros to make header files cleaner
- *
- * To completely disable CCSR relocation in a board header file, define
- * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
- * to a value that is the same as CONFIG_SYS_CCSRBAR.
- */
-
-#ifdef CONFIG_SYS_CCSRBAR_PHYS
-#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
-#endif
-
-#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
-#endif
-
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
#endif
diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h
index 0a626fe..4054dd8ed 100644
--- a/arch/arm/include/asm/arch-omap4/clock.h
+++ b/arch/arm/include/asm/arch-omap4/clock.h
@@ -7,7 +7,6 @@
*/
#ifndef _CLOCKS_OMAP4_H_
#define _CLOCKS_OMAP4_H_
-#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index a00626e..b18ef45 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -8,7 +8,6 @@
*/
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
-#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
diff --git a/arch/arm/include/asm/arch-pxa/config.h b/arch/arm/include/asm/arch-pxa/config.h
index 75b0e49..11effd4 100644
--- a/arch/arm/include/asm/arch-pxa/config.h
+++ b/arch/arm/include/asm/arch-pxa/config.h
@@ -13,8 +13,6 @@
*/
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define CONFIG_SYS_TIMER_RATE 3250000
-#elif defined(CONFIG_CPU_PXA25X)
-#define CONFIG_SYS_TIMER_RATE 3686400
#else
#error "Timer frequency unknown - please config PXA CPU type"
#endif
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 14860d8..26f1877 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -11,7 +11,6 @@
#if defined(CONFIG_ARCH_LS1021A) || \
defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \
- defined(CONFIG_CPU_PXA25X) || \
defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/config.h>
#endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 264a2e7..17fdfbc 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -13,6 +13,7 @@
#include <linux/types.h>
#define NUM_SYS_CLKS 7
+#define SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
struct bd_info;
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 612a2d5..fe6b447 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -9,6 +9,7 @@
#include <asm-offsets.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <system-constants.h>
/*
* This file handles the target-independent stages of the U-Boot
@@ -104,7 +105,7 @@
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
- ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
+ ldr r0, =(SYS_INIT_SP_ADDR)
#endif
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 84c04bd..dcc924d 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -13,6 +13,7 @@
#include <asm-offsets.h>
#include <asm/macro.h>
#include <linux/linkage.h>
+#include <system-constants.h>
/*
* This file handles the target-independent stages of the U-Boot
@@ -81,7 +82,7 @@
#endif
add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
#else
- ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
+ ldr x0, =(SYS_INIT_SP_ADDR)
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
mov x0, sp
diff --git a/arch/arm/lib/vectors_m.S b/arch/arm/lib/vectors_m.S
index 7d2d55c..8d88cc7 100644
--- a/arch/arm/lib/vectors_m.S
+++ b/arch/arm/lib/vectors_m.S
@@ -7,6 +7,7 @@
#include <config.h>
#include <asm/assembler.h>
#include <linux/linkage.h>
+#include <system-constants.h>
.type __hard_fault_entry, %function
__hard_fault_entry:
@@ -35,7 +36,7 @@
.section .vectors
ENTRY(_start)
- .long CONFIG_SYS_INIT_SP_ADDR @ 0 - Reset stack pointer
+ .long SYS_INIT_SP_ADDR @ 0 - Reset stack pointer
.long reset @ 1 - Reset
.long __invalid_entry @ 2 - NMI
.long __hard_fault_entry @ 3 - HardFault
diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig
new file mode 100644
index 0000000..2d49380
--- /dev/null
+++ b/arch/arm/mach-bcmbca/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if ARCH_BCMBCA
+
+config BCM47622
+ bool "Support for Broadcom 47622 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+endif
+
+source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile
new file mode 100644
index 0000000..072d4ea
--- /dev/null
+++ b/arch/arm/mach-bcmbca/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+obj-$(CONFIG_BCM47622) += bcm47622/
diff --git a/arch/arm/mach-bcmbca/bcm47622/Kconfig b/arch/arm/mach-bcmbca/bcm47622/Kconfig
new file mode 100644
index 0000000..bce3089
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm47622/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM47622
+
+config TARGET_BCM947622
+ bool "Broadcom 47622 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm47622"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm47622/Makefile b/arch/arm/mach-bcmbca/bcm47622/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm47622/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index a01bf23..57f693e 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -16,6 +16,9 @@
config SOC_K3_AM642
bool "TI's K3 based AM642 SoC Family Support"
+config SOC_K3_AM625
+ bool "TI's K3 based AM625 SoC Family Support"
+
endchoice
config SYS_SOC
@@ -26,6 +29,7 @@
default 0x80000 if SOC_K3_AM6
default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x1c0000 if SOC_K3_AM642
+ default 0x3c000 if SOC_K3_AM625
help
Describes the total size of the MCU or OCMC MSRAM present on
the SoC in use. This doesn't specify the total size of SPL as
@@ -37,6 +41,7 @@
default 0x58000 if SOC_K3_AM6
default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
default 0x180000 if SOC_K3_AM642
+ default 0x38000 if SOC_K3_AM625
help
Describes the maximum size of the image that ROM can download
from any boot media.
@@ -61,6 +66,7 @@
default 0x41cffbfc if SOC_K3_J721E
default 0x41cfdbfc if SOC_K3_J721S2
default 0x701bebfc if SOC_K3_AM642
+ default 0x43c3f290 if SOC_K3_AM625
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@@ -129,6 +135,7 @@
config K3_SYSFW_IMAGE_SIZE_MAX
int "Amount of memory dynamically allocated for loading SYSFW blob"
depends on K3_LOAD_SYSFW
+ default 163840 if SOC_K3_AM625
default 278000
help
Amount of memory (in bytes) reserved through dynamic allocation at
@@ -160,7 +167,7 @@
config K3_DM_FW
bool "Separate DM firmware image"
- depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
+ depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
@@ -171,6 +178,7 @@
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
+source "board/ti/am62x/Kconfig"
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
source "board/ti/j721s2/Kconfig"
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index c0a6a9c..8459bef 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
+obj-$(CONFIG_SOC_K3_AM625) += am625_init.o am62x/
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
new file mode 100644
index 0000000..0d95259
--- /dev/null
+++ b/arch/arm/mach-k3/am625_init.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM625: SoC specific initialization
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Suman Anna <s-anna@ti.com>
+ */
+
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include "common.h"
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 4);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
+
+ /* Unlock PADCFG_CTRL_MMR padconf registers */
+ mmr_unlock(PADCFG_MMR0_BASE, 1);
+ mmr_unlock(PADCFG_MMR1_BASE, 1);
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+#if defined(CONFIG_CPU_V7R)
+ setup_k3_mpu_regions();
+#endif
+
+ /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+ */
+ store_boot_info_from_rom();
+
+ ctrl_mmr_unlock();
+
+ /* Init DM early */
+ spl_early_init();
+
+ /*
+ * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
+ * MAIN_UART1 modules and continue regardless of the result of pinctrl.
+ * Do this without probing the device, but instead by searching the
+ * device that would request the given sequence number if probed. The
+ * UARTs will be used by the DM firmware and TIFS firmware images
+ * respectively and the firmware depend on SPL to initialize the pin
+ * settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ preloader_console_init();
+
+#ifdef CONFIG_K3_EARLY_CONS
+ /*
+ * Allow establishing an early console as required for example when
+ * doing a UART-based boot. Note that this console may not "survive"
+ * through a SYSFW PM-init step and will need a re-init in some way
+ * due to changing module clock frequencies.
+ */
+ early_console_init();
+#endif
+
+#if defined(CONFIG_K3_LOAD_SYSFW)
+ /*
+ * Configure and start up system controller firmware. Provide
+ * the U-Boot console init function to the SYSFW post-PM configuration
+ * callback hook, effectively switching on (or over) the console
+ * output.
+ */
+ ret = is_rom_loaded_sysfw(&bootdata);
+ if (!ret)
+ panic("ROM has not loaded TIFS firmware\n");
+
+ k3_sysfw_loader(true, NULL, NULL);
+#endif
+
+ /*
+ * Force probe of clk_k3 driver here to ensure basic default clock
+ * configuration is always done.
+ */
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ &dev);
+ if (ret)
+ printf("Failed to initialize clk-k3!\n");
+ }
+
+ /* Output System Firmware version info */
+ k3_sysfw_print_ver();
+
+#if defined(CONFIG_K3_AM64_DDRSS)
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("DRAM init failed: %d\n", ret);
+#endif
+}
+
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+ u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT)
+ return MMCSD_MODE_EMMCBOOT;
+ return MMCSD_MODE_FS;
+
+ case BOOT_DEVICE_MMC2:
+ return MMCSD_MODE_FS;
+
+ default:
+ return MMCSD_MODE_RAW;
+ }
+}
+
+static u32 __get_backup_bootmedia(u32 devstat)
+{
+ u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+ u32 bkup_bootmode_cfg =
+ (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+
+ case BACKUP_BOOT_DEVICE_USB:
+ return BOOT_DEVICE_USB;
+
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+
+ case BACKUP_BOOT_DEVICE_DFU:
+ if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+ };
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 devstat)
+{
+ u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+ u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ fallthrough;
+ case BOOT_DEVICE_QSPI:
+ fallthrough;
+ case BOOT_DEVICE_XSPI:
+ fallthrough;
+ case BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BOOT_DEVICE_ETHERNET_RGMII:
+ fallthrough;
+ case BOOT_DEVICE_ETHERNET_RMII:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BOOT_DEVICE_EMMC:
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_MMC:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_DFU:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+
+ case BOOT_DEVICE_NOBOOT:
+ return BOOT_DEVICE_RAM;
+ }
+
+ return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+ u32 bootmedia;
+
+ if (bootindex == K3_PRIMARY_BOOTMODE)
+ bootmedia = __get_primary_bootmedia(devstat);
+ else
+ bootmedia = __get_backup_bootmedia(devstat);
+
+ debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
+ __func__, devstat, bootmedia, bootindex);
+
+ return bootmedia;
+}
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile
new file mode 100644
index 0000000..d6c876d
--- /dev/null
+++ b/arch/arm/mach-k3/am62x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c
new file mode 100644
index 0000000..c088177
--- /dev/null
+++ b/arch/arm/mach-k3/am62x/clk-data.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AM62X specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Dave Gerlach <d-gerlach@ti.com>.
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ NULL,
+ NULL,
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ NULL,
+};
+
+static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc0_clklb_out",
+ "board_0_mmc0_clk_out",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+ "board_0_ospi0_dqs_out",
+ "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const main_usb1_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
+ "clk_32k_rc_sel_div_clkout",
+ "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout1_clk",
+ "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_clkout_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "gluelogic_lfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "postdiv4_16ff_main_2_hsdivout9_clk",
+ "clk_32k_rc_sel_out0",
+ "gluelogic_rcosc_clkout",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const wkup_clksel_out0_parents[] = {
+ "hsdiv1_16fft_main_15_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const main_usart0_fclk_sel_out0_parents[] = {
+ "usart_programmable_clock_divider_out0",
+ "hsdiv4_16fft_main_1_hsdivout1_clk",
+};
+
+static const struct clk_data clk_list[] = {
+ CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+ CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+ CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+ CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+ CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
+ CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
+ CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+ CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
+ CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+ CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
+ CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
+ CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
+ CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
+ CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
+ CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
+ CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
+ CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
+ CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
+ CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
+ CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
+ CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
+ CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
+ CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
+ CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
+ CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
+ CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
+ CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
+ CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
+ CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
+ CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
+ CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
+ CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
+ CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
+ CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
+ CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
+ CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
+ DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
+ DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
+ DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
+ DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
+ DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+ DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+ DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
+ DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
+ DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
+ DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
+ DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
+ DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
+ DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
+ DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
+ DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
+ DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
+ DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
+ DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
+ DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
+ DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
+ DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
+ DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 9, "wkup_clksel_out0"),
+ DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
+ DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
+ DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
+ DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
+ DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
+ DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
+ DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
+ DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
+ DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(95, 2, "wkup_clksel_out0"),
+ DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
+ DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
+ DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
+ DEV_CLK(107, 0, "wkup_clksel_out0"),
+ DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
+ DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
+ DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
+ DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
+ DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
+ DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
+ DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 20, "clkout0_ctrl_out0"),
+ DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
+ DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
+ DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
+ DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
+ DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
+ DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
+ DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
+ DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
+ DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
+ DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
+ DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
+ DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
+ DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
+ DEV_CLK(161, 10, "board_0_tck_out"),
+ DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
+ DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
+ DEV_CLK(162, 10, "board_0_tck_out"),
+ DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(170, 1, "board_0_tck_out"),
+ DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+};
+
+const struct ti_k3_clk_platdata am62x_clk_platdata = {
+ .clk_list = clk_list,
+ .clk_list_cnt = 90,
+ .soc_dev_clk_data = soc_dev_clk_data,
+ .soc_dev_clk_data_cnt = 137,
+};
diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c
new file mode 100644
index 0000000..616d065
--- /dev/null
+++ b/arch/arm/mach-k3/am62x/dev-data.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AM62X specific device platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Dave Gerlach <d-gerlach@ti.com>.
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+ [0] = PSC(0, 0x04000000),
+ [1] = PSC(1, 0x00400000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+ [0] = PSC_PD(0, &soc_psc_list[1], NULL),
+ [1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
+ [2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
+ [3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
+ [4] = PSC_PD(5, &soc_psc_list[1], &soc_pd_list[2]),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+ [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
+ [1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+ [2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]),
+ [3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]),
+ [4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
+ [5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]),
+ [6] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+ [7] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+ [8] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+ [9] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+ [10] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+ [11] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+ [12] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[11]),
+ [13] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[11]),
+ [14] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[13]),
+ [15] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
+};
+
+static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(16, &soc_lpsc_list[0]),
+ PSC_DEV(77, &soc_lpsc_list[0]),
+ PSC_DEV(61, &soc_lpsc_list[0]),
+ PSC_DEV(95, &soc_lpsc_list[0]),
+ PSC_DEV(107, &soc_lpsc_list[0]),
+ PSC_DEV(170, &soc_lpsc_list[1]),
+ PSC_DEV(177, &soc_lpsc_list[2]),
+ PSC_DEV(55, &soc_lpsc_list[3]),
+ PSC_DEV(178, &soc_lpsc_list[4]),
+ PSC_DEV(179, &soc_lpsc_list[5]),
+ PSC_DEV(57, &soc_lpsc_list[6]),
+ PSC_DEV(58, &soc_lpsc_list[7]),
+ PSC_DEV(161, &soc_lpsc_list[8]),
+ PSC_DEV(162, &soc_lpsc_list[9]),
+ PSC_DEV(75, &soc_lpsc_list[10]),
+ PSC_DEV(102, &soc_lpsc_list[11]),
+ PSC_DEV(146, &soc_lpsc_list[11]),
+ PSC_DEV(13, &soc_lpsc_list[12]),
+ PSC_DEV(166, &soc_lpsc_list[13]),
+ PSC_DEV(135, &soc_lpsc_list[14]),
+ PSC_DEV(136, &soc_lpsc_list[15]),
+};
+
+const struct ti_k3_pd_platdata am62x_pd_platdata = {
+ .psc = soc_psc_list,
+ .pd = soc_pd_list,
+ .lpsc = soc_lpsc_list,
+ .devs = soc_dev_list,
+ .num_psc = 2,
+ .num_pd = 5,
+ .num_lpsc = 16,
+ .num_devs = 21,
+};
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 86c1a34..7992918 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -127,8 +127,8 @@
* before the dwc3 bind takes place
*/
ret = fdt_find_and_setprop((void *)gd->fdt_blob,
- "/interconnect@100000/dwc3@4000000/usb@10000",
- "dr_mode", "host", 11, 0);
+ "/bus@100000/dwc3@4000000/usb@10000",
+ "dr_mode", "host", 5, 0);
if (ret)
printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
ret);
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 527e664..12cb893 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -222,7 +222,7 @@
#endif /* CONFIG_SOC_K3_J721S2 */
-#ifdef CONFIG_SOC_K3_AM642
+#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625))
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
@@ -261,4 +261,4 @@
};
struct mm_region *mem_map = am64_mem_map;
-#endif /* CONFIG_SOC_K3_AM642 */
+#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 */
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h
new file mode 100644
index 0000000..cfabd20
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM62 SoC definitions, structures etc.
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Suman Anna <s-anna@ti.com>
+ */
+
+#ifndef __ASM_ARCH_AM62_HARDWARE_H
+#define __ASM_ARCH_AM62_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define PADCFG_MMR0_BASE 0x04080000
+#define PADCFG_MMR1_BASE 0x000f0000
+#define CTRL_MMR0_BASE 0x00100000
+#define MCU_CTRL_MMR0_BASE 0x04500000
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+
+#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
+
+/* Primary Bootmode MMC Config macros */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
+#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
+#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
+
+/* Primary Bootmode USB Config macros */
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
+
+/* Backup Bootmode USB Config macros */
+#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
+ * shared register definitions. The same registers are also used for
+ * PADCFG_MMR lock/kick-mechanism.
+ */
+#define CTRLMMR_LOCK_KICK0 0x1008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK1 0x100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
+#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
+#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
+#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
+
+#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
+#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
+
+#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0
+
+/* Use Last 2K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000000
+
+#endif /* __ASM_ARCH_AM62_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am62_spl.h b/arch/arm/mach-k3/include/mach/am62_spl.h
new file mode 100644
index 0000000..2c9139d
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am62_spl.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Suman Anna <s-anna@ti.com>
+ */
+
+#ifndef _ASM_ARCH_AM62_SPL_H_
+#define _ASM_ARCH_AM62_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_CPGMAC 0x04
+#define BOOT_DEVICE_ETHERNET_RGMII 0x04
+#define BOOT_DEVICE_ETHERNET_RMII 0x05
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_MMC 0x08
+#define BOOT_DEVICE_EMMC 0x09
+
+#define BOOT_DEVICE_USB 0x2A
+#define BOOT_DEVICE_DFU 0x0A
+#define BOOT_DEVICE_GPMC_NAND 0x0B
+#define BOOT_DEVICE_GPMC_NOR 0x0C
+#define BOOT_DEVICE_XSPI 0x0E
+#define BOOT_DEVICE_NOBOOT 0x0F
+
+/* U-Boot used aliases */
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_MMC2 0x08
+#define BOOT_DEVICE_MMC1 0x09
+/* Invalid */
+#define BOOT_DEVICE_MMC2_2 0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_DFU 0x01
+#define BACKUP_BOOT_DEVICE_UART 0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
+#define BACKUP_BOOT_DEVICE_MMC 0x05
+#define BACKUP_BOOT_DEVICE_SPI 0x06
+#define BACKUP_BOOT_DEVICE_I2C 0x07
+#define BACKUP_BOOT_DEVICE_USB 0x09
+
+#define K3_PRIMARY_BOOTMODE 0x0
+
+#endif /* _ASM_ARCH_AM62_SPL_H_ */
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 5c1265f..7c6928d 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -22,6 +22,10 @@
#include "am64_hardware.h"
#endif
+#ifdef CONFIG_SOC_K3_AM625
+#include "am62_hardware.h"
+#endif
+
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
#define JTAG_ID_VARIANT_SHIFT 28
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index 8a61398..17996f2 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -21,4 +21,9 @@
#ifdef CONFIG_SOC_K3_AM642
#include "am64_spl.h"
#endif
+
+#ifdef CONFIG_SOC_K3_AM625
+#include "am62_spl.h"
+#endif
+
#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 5e48c36..988e758 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -346,6 +346,25 @@
}
#endif
+#if CONFIG_IS_ENABLED(NOR_SUPPORT)
+static void *get_sysfw_hf_addr(void)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_find_first_device(UCLASS_MTD, &dev);
+ if (ret)
+ return NULL;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+}
+#endif
+
void k3_sysfw_loader(bool rom_loaded_sysfw,
void (*config_pm_pre_callback)(void),
void (*config_pm_done_callback)(void))
@@ -413,6 +432,15 @@
CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
break;
#endif
+#if CONFIG_IS_ENABLED(NOR_SUPPORT)
+ case BOOT_DEVICE_HYPERFLASH:
+ sysfw_spi_base = get_sysfw_hf_addr();
+ if (!sysfw_spi_base)
+ ret = -ENODEV;
+ k3_sysfw_spi_copy(sysfw_load_address, sysfw_spi_base,
+ CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+ break;
+#endif
#if CONFIG_IS_ENABLED(YMODEM_SUPPORT)
case BOOT_DEVICE_UART:
#ifdef CONFIG_K3_EARLY_CONS
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 7810cf2..45ee027 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -27,9 +27,6 @@
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-/* Kirkwood has 2k of Security SRAM, use it for SP */
-#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
-
#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
#define MV_UART_CONSOLE_BASE KW_UART0_BASE
#define MV_SATA_BASE KW_SATA_BASE
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 8bd2246..61eeb9c 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -65,10 +65,12 @@
KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
KWB_REPLACE += SEC_BOOT_DEV
-KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
- $(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
- $(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
- )
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),)
+ KWB_CFG_SEC_BOOT_DEV=0x34
+endif
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC),)
+ KWB_CFG_SEC_BOOT_DEV=0x31
+endif
KWB_REPLACE += SEC_FUSE_DUMP
KWB_CFG_SEC_FUSE_DUMP = a38x
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index fb4e5af..4add0d9 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -27,9 +27,6 @@
#define CONFIG_SYS_L2_PL310
-/* end of 16M scrubbed by training in bootrom */
-#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
-
#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
/* Needed for SPI NOR booting in SPL */
diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S
index 501c239..49891df9 100644
--- a/arch/arm/mach-mvebu/lowlevel_spl.S
+++ b/arch/arm/mach-mvebu/lowlevel_spl.S
@@ -8,19 +8,19 @@
* contains U-Boot SPL, optionally it can also contain additional arguments.
* The number of these arguments is in r0, pointer to the argument array in r1.
* BootROM expects executable BIN header code to return to address stored in lr.
- * Other registers (r2 - r12) must be preserved. We save all registers to
- * CONFIG_SPL_BOOTROM_SAVE address. BIN header arguments (passed via r0 and r1)
+ * Other registers (r2 - r12) must be preserved. We save all registers to the
+ * address of CONFIG_SPL_STACK + 4. BIN header arguments (passed via r0 and r1)
* are currently not used by U-Boot SPL binary.
*/
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
- ldr r12, =CONFIG_SPL_BOOTROM_SAVE
+ ldr r12, =(CONFIG_SPL_STACK + 4)
str sp, [r12]
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(return_to_bootrom)
- ldr r12, =CONFIG_SPL_BOOTROM_SAVE
+ ldr r12, =(CONFIG_SPL_STACK + 4)
ldr sp, [r12]
ldmfd sp!, {r0 - r12, lr} /* @ restore registers from stack */
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index fa9a1d7..13c9991 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -283,7 +283,7 @@
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- u32 *regs = *(u32 **)CONFIG_SPL_BOOTROM_SAVE;
+ u32 *regs = *(u32 **)(CONFIG_SPL_STACK + 4);
printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]);
return_to_bootrom();
diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c
index 4672dc5..53c39ce 100644
--- a/arch/arm/mach-omap2/sata.c
+++ b/arch/arm/mach-omap2/sata.c
@@ -13,6 +13,7 @@
#include <asm/arch/sata.h>
#include <sata.h>
#include <asm/io.h>
+#include <asm/omap_common.h>
#include "pipe3-phy.h"
static struct pipe3_dpll_map dpll_map_sata[] = {
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 82b10f6..00d91c1 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -22,6 +22,7 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
+#include <asm/omap_common.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,7 +34,7 @@
* Nothing really to do with interrupts, just starts up a counter.
*/
-#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
+#define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV))
#define TIMER_OVERFLOW_VAL 0xffffffff
#define TIMER_LOAD_VAL 0
@@ -42,7 +43,7 @@
/* start the counter ticking up, reload value on overflow */
writel(TIMER_LOAD_VAL, &timer_base->tldr);
/* enable timer */
- writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+ writel((SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
&timer_base->tclr);
return 0;
diff --git a/arch/arm/mach-rmobile/lowlevel_init.S b/arch/arm/mach-rmobile/lowlevel_init.S
index eb6012a..212e955 100644
--- a/arch/arm/mach-rmobile/lowlevel_init.S
+++ b/arch/arm/mach-rmobile/lowlevel_init.S
@@ -6,6 +6,7 @@
#include <config.h>
#include <linux/linkage.h>
+#include <system-constants.h>
ENTRY(lowlevel_init)
ldr r0, =MERAM_BASE
diff --git a/arch/arm/mach-rmobile/lowlevel_init_ca15.S b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
index 967fb02..a52b761 100644
--- a/arch/arm/mach-rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
@@ -8,6 +8,7 @@
#include <config.h>
#include <linux/linkage.h>
+#include <system-constants.h>
ENTRY(lowlevel_init)
#ifndef CONFIG_SPL_BUILD
@@ -75,7 +76,7 @@
#endif
_exit_init_l2_a15:
- ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
+ ldr r3, =(SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index 4886fe9..28639c0 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -56,9 +56,6 @@
config TPL_TEXT_BASE
default 0xff0e1000
-config TPL_MAX_SIZE
- default 10240
-
config TPL_STACK
default 0xff0e4fff
diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig
index 058f848..9ad1f54 100644
--- a/arch/arm/mach-rockchip/rk322x/Kconfig
+++ b/arch/arm/mach-rockchip/rk322x/Kconfig
@@ -26,9 +26,6 @@
config SPL_SERIAL
default y
-config TPL_MAX_SIZE
- default 28672
-
config TPL_STACK
default 0x10088000
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index dd8c782..e8c5784 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -172,9 +172,6 @@
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl.lds"
-config TPL_MAX_SIZE
- default 32768
-
config TPL_STACK
default 0xff718000
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
index f6f1e06..d5cb649 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -36,9 +36,6 @@
config TPL_TEXT_BASE
default 0xff091000
-config TPL_MAX_SIZE
- default 28672
-
config TPL_STACK
default 0xff098000
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index 104db36..25afd3c 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -71,9 +71,6 @@
config SPL_STACK_R_ADDR
default 0x04000000
-config TPL_MAX_SIZE
- default 28672
-
config TPL_STACK
default 0xff8cffff
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index c1f2513..b48feeb 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -143,9 +143,6 @@
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
-config TPL_MAX_SIZE
- default 188416
-
config TPL_STACK
default 0xff8effff
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index f9a583a..d9e2640 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -9,7 +9,7 @@
config TARGET_STIH410_B2260
bool "96Boards STiH410-B2260"
help
- Support for 96Board STiH410-B2260 based on STMicrolectronics
+ Support for 96Board STiH410-B2260 based on STMicroelectronics
STiH410 soc. This board complies with 96Board Open Platform
Specifications. Features:
- 1GB DDR
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index e48f98b..db47bab 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -33,6 +33,28 @@
config ENV_SIZE
default 0x2000
+choice
+ prompt "Select STMicroelectronics STM32MPxxx Soc"
+ default STM32MP15x
+
+config STM32MP13x
+ bool "Support STMicroelectronics STM32MP13x Soc"
+ select ARM_SMCCC
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select OF_BOARD
+ select OF_BOARD_SETUP
+ select PINCTRL_STM32
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
+ select SYS_ARCH_TIMER
+ imply CMD_NVEDIT_INFO
+ help
+ support of STMicroelectronics SOC STM32MP13x family
+ STMicroelectronics MPU with core ARMv7
+
config STM32MP15x
bool "Support STMicroelectronics STM32MP15x Soc"
select ARCH_SUPPORT_PSCI
@@ -46,6 +68,7 @@
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
+ select SUPPORT_SPL
select SYS_ARCH_TIMER
imply CMD_NVEDIT_INFO
help
@@ -53,92 +76,8 @@
STM32MP157, STM32MP153 or STM32MP151
STMicroelectronics MPU with core ARMv7
dual core A7 for STM32MP157/3, monocore for STM32MP151
- target all the STMicroelectronics board with SOC STM32MP1 family
-
-config STM32MP15x_STM32IMAGE
- bool "Support STM32 image for generated U-Boot image"
- depends on STM32MP15x && TFABOOT
- help
- Support of STM32 image generation for SOC STM32MP15x
- for TF-A boot when FIP container is not used
-
-choice
- prompt "STM32MP15x board select"
- optional
-
-config TARGET_ST_STM32MP15x
- bool "STMicroelectronics STM32MP15x boards"
- select STM32MP15x
- imply BOOTSTAGE
- imply CMD_BOOTSTAGE
- imply CMD_CLS if CMD_BMP
- imply DISABLE_CONSOLE
- imply PRE_CONSOLE_BUFFER
- imply SILENT_CONSOLE
- help
- target the STMicroelectronics board with SOC STM32MP15x
- managed by board/st/stm32mp1:
- Evalulation board (EV1) or Discovery board (DK1 and DK2).
- The difference between board are managed with devicetree
-
-config TARGET_MICROGEA_STM32MP1
- bool "Engicam MicroGEA STM32MP1 SOM"
- select STM32MP15x
- imply BOOTSTAGE
- imply CMD_BOOTSTAGE
- imply CMD_CLS if CMD_BMP
- imply DISABLE_CONSOLE
- imply PRE_CONSOLE_BUFFER
- imply SILENT_CONSOLE
- help
- MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
-
- MicroGEA STM32MP1 MicroDev 2.0:
- * MicroDev 2.0 is a general purpose miniature carrier board with CAN,
- LTE and LVDS panel interfaces.
- * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
- for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
-
- MicroGEA STM32MP1 MicroDev 2.0 7" OF:
- * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
- panel and toucscreen.
- * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
- pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
- Open Frame Solution board.
-
-config TARGET_ICORE_STM32MP1
- bool "Engicam i.Core STM32MP1 SOM"
- select STM32MP15x
- imply BOOTSTAGE
- imply CMD_BOOTSTAGE
- imply CMD_CLS if CMD_BMP
- imply DISABLE_CONSOLE
- imply PRE_CONSOLE_BUFFER
- imply SILENT_CONSOLE
- help
- i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
-
- i.Core STM32MP1 EDIMM2.2:
- * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
- * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
- creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
-
- i.Core STM32MP1 C.TOUCH 2.0
- * C.TOUCH 2.0 is a general purpose Carrier board.
- * i.Core STM32MP1 needs to mount on top of this Carrier board
- for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
-
-config TARGET_DH_STM32MP1_PDK2
- bool "DH STM32MP1 PDK2"
- select STM32MP15x
- help
- Target the DH PDK2 development kit with STM32MP15x SoM.
-
endchoice
-config SYS_TEXT_BASE
- default 0xC0100000
-
config NR_DRAM_BANKS
default 1
@@ -164,7 +103,7 @@
config STM32_ETZPC
bool "STM32 Extended TrustZone Protection"
- depends on STM32MP15x
+ depends on STM32MP15x || STM32MP13x
default y
imply BOOTP_SERVERIP
help
@@ -187,41 +126,8 @@
This command is used to evaluate the secure boot on stm32mp SOC,
it is deactivated by default in real products.
-config PRE_CON_BUF_ADDR
- default 0xC02FF000
-
-config PRE_CON_BUF_SZ
- default 4096
-
-config BOOTSTAGE_STASH_ADDR
- default 0xC3000000
-
-if BOOTCOUNT_GENERIC
-config SYS_BOOTCOUNT_SINGLEWORD
- default y
-
-# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
-config SYS_BOOTCOUNT_ADDR
- default 0x5C00A154
-endif
-
-if DEBUG_UART
-
-config DEBUG_UART_BOARD_INIT
- default y
-
-# debug on UART4 by default
-config DEBUG_UART_BASE
- default 0x40010000
-
-# clock source is HSI on reset
-config DEBUG_UART_CLOCK
- default 64000000
-endif
+source "arch/arm/mach-stm32mp/Kconfig.13x"
+source "arch/arm/mach-stm32mp/Kconfig.15x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
-source "board/dhelectronics/dh_stm32mp1/Kconfig"
-source "board/engicam/stm32mp1/Kconfig"
-source "board/st/stm32mp1/Kconfig"
-
endif
diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x
new file mode 100644
index 0000000..5fc0009
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Kconfig.13x
@@ -0,0 +1,57 @@
+if STM32MP13x
+
+choice
+ prompt "STM32MP13x board select"
+ optional
+
+config TARGET_ST_STM32MP13x
+ bool "STMicroelectronics STM32MP13x boards"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ imply CMD_CLS if CMD_BMP
+ imply DISABLE_CONSOLE
+ imply PRE_CONSOLE_BUFFER
+ imply SILENT_CONSOLE
+ help
+ target the STMicroelectronics board with SOC STM32MP13x
+ managed by board/st/stm32mp1.
+ The difference between board are managed with devicetree
+
+endchoice
+
+config SYS_TEXT_BASE
+ default 0xC0000000
+
+config PRE_CON_BUF_ADDR
+ default 0xC0800000
+
+config PRE_CON_BUF_SZ
+ default 4096
+
+config BOOTSTAGE_STASH_ADDR
+ default 0xC3000000
+
+if BOOTCOUNT_GENERIC
+config SYS_BOOTCOUNT_SINGLEWORD
+ default y
+
+# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(31)
+config SYS_BOOTCOUNT_ADDR
+ default 0x5C00A17C
+endif
+
+if DEBUG_UART
+
+# debug on UART4 by default
+config DEBUG_UART_BASE
+ default 0x40010000
+
+# clock source is HSI on reset
+config DEBUG_UART_CLOCK
+ default 48000000 if STM32_FPGA
+ default 64000000
+endif
+
+source "board/st/stm32mp1/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x
new file mode 100644
index 0000000..d516270
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Kconfig.15x
@@ -0,0 +1,135 @@
+if STM32MP15x
+
+config STM32MP15x_STM32IMAGE
+ bool "Support STM32 image for generated U-Boot image"
+ depends on TFABOOT
+ help
+ Support of STM32 image generation for SOC STM32MP15x
+ for TF-A boot when FIP container is not used
+
+choice
+ prompt "STM32MP15x board select"
+ optional
+
+config TARGET_ST_STM32MP15x
+ bool "STMicroelectronics STM32MP15x boards"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ imply CMD_CLS if CMD_BMP
+ imply DISABLE_CONSOLE
+ imply PRE_CONSOLE_BUFFER
+ imply SILENT_CONSOLE
+ help
+ target the STMicroelectronics board with SOC STM32MP15x
+ managed by board/st/stm32mp1:
+ Evalulation board (EV1) or Discovery board (DK1 and DK2).
+ The difference between board are managed with devicetree
+
+config TARGET_DH_STM32MP1_PDK2
+ bool "DH STM32MP1 PDK2"
+ help
+ Target the DH PDK2 development kit with STM32MP15x SoM.
+
+config TARGET_MICROGEA_STM32MP1
+ bool "Engicam MicroGEA STM32MP1 SOM"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ imply CMD_CLS if CMD_BMP
+ imply DISABLE_CONSOLE
+ imply PRE_CONSOLE_BUFFER
+ imply SILENT_CONSOLE
+ help
+ MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
+
+ MicroGEA STM32MP1 MicroDev 2.0:
+ * MicroDev 2.0 is a general purpose miniature carrier board with CAN,
+ LTE and LVDS panel interfaces.
+ * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
+ for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
+
+ MicroGEA STM32MP1 MicroDev 2.0 7" OF:
+ * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
+ panel and toucscreen.
+ * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
+ pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
+ Open Frame Solution board.
+
+config TARGET_ICORE_STM32MP1
+ bool "Engicam i.Core STM32MP1 SOM"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ imply CMD_CLS if CMD_BMP
+ imply DISABLE_CONSOLE
+ imply PRE_CONSOLE_BUFFER
+ imply SILENT_CONSOLE
+ help
+ i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
+
+ i.Core STM32MP1 EDIMM2.2:
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
+ * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
+ creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
+
+ i.Core STM32MP1 C.TOUCH 2.0
+ * C.TOUCH 2.0 is a general purpose Carrier board.
+ * i.Core STM32MP1 needs to mount on top of this Carrier board
+ for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
+
+endchoice
+
+config STM32MP15_PWR
+ bool "Enable driver for STM32MP15x PWR"
+ depends on DM_REGULATOR && DM_PMIC
+ default y
+ help
+ This config enables implementation of driver-model pmic and
+ regulator uclass features for access to STM32MP15x PWR.
+
+config SPL_STM32MP15_PWR
+ bool "Enable driver for STM32MP15x PWR in SPL"
+ depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC
+ default y
+ help
+ This config enables implementation of driver-model pmic and
+ regulator uclass features for access to STM32MP15x PWR in SPL.
+
+config SYS_TEXT_BASE
+ default 0xC0100000
+
+config PRE_CON_BUF_ADDR
+ default 0xC02FF000
+
+config PRE_CON_BUF_SZ
+ default 4096
+
+config BOOTSTAGE_STASH_ADDR
+ default 0xC3000000
+
+if BOOTCOUNT_GENERIC
+config SYS_BOOTCOUNT_SINGLEWORD
+ default y
+
+# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
+config SYS_BOOTCOUNT_ADDR
+ default 0x5C00A154
+endif
+
+if DEBUG_UART
+
+config DEBUG_UART_BOARD_INIT
+ default y
+
+# debug on UART4 by default
+config DEBUG_UART_BASE
+ default 0x40010000
+
+# clock source is HSI on reset
+config DEBUG_UART_CLOCK
+ default 64000000
+endif
+
+source "board/st/stm32mp1/Kconfig"
+source "board/dhelectronics/dh_stm32mp1/Kconfig"
+source "board/engicam/stm32mp1/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 391b47c..1db9057 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -8,6 +8,9 @@
obj-y += syscon.o
obj-y += bsec.o
+obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
+obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
+
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += tzc400.o
@@ -19,5 +22,5 @@
obj-$(CONFIG_TFABOOT) += boot_params.o
endif
-obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
+obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 506caa0..c00130b 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -632,3 +632,20 @@
return false;
}
+
+u32 get_otp(int index, int shift, int mask)
+{
+ int ret;
+ struct udevice *dev;
+ u32 otp = 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(stm32mp_bsec),
+ &dev);
+
+ if (!ret)
+ ret = misc_read(dev, STM32_BSEC_SHADOW(index),
+ &otp, sizeof(otp));
+
+ return (otp >> shift) & mask;
+}
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 0ad5f30..855fc75 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -16,7 +16,6 @@
#include <misc.h>
#include <net.h>
#include <asm/io.h>
-#include <asm/arch/bsec.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
@@ -24,67 +23,6 @@
#include <dm/uclass.h>
#include <linux/bitops.h>
-/* RCC register */
-#define RCC_TZCR (STM32_RCC_BASE + 0x00)
-#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
-#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
-#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
-#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
-#define RCC_BDCR_VSWRST BIT(31)
-#define RCC_BDCR_RTCSRC GENMASK(17, 16)
-#define RCC_DBGCFGR_DBGCKEN BIT(8)
-
-/* Security register */
-#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
-#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
-
-#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
-#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
-#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
-
-#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
-
-#define PWR_CR1 (STM32_PWR_BASE + 0x00)
-#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
-#define PWR_CR1_DBP BIT(8)
-#define PWR_MCUCR_SBF BIT(6)
-
-/* DBGMCU register */
-#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
-#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
-#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
-#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
-#define DBGMCU_IDC_DEV_ID_SHIFT 0
-#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
-#define DBGMCU_IDC_REV_ID_SHIFT 16
-
-/* GPIOZ registers */
-#define GPIOZ_SECCFGR 0x54004030
-
-/* boot interface from Bootrom
- * - boot instance = bit 31:16
- * - boot device = bit 15:0
- */
-#define BOOTROM_PARAM_ADDR 0x2FFC0078
-#define BOOTROM_MODE_MASK GENMASK(15, 0)
-#define BOOTROM_MODE_SHIFT 0
-#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
-#define BOOTROM_INSTANCE_SHIFT 16
-
-/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
-#define RPN_SHIFT 0
-#define RPN_MASK GENMASK(7, 0)
-
-/* Package = bit 27:29 of OTP16
- * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
- * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
- * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
- * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
- * - others: Reserved
- */
-#define PKG_SHIFT 27
-#define PKG_MASK GENMASK(2, 0)
-
/*
* early TLB into the .data section so that it not get cleared
* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
@@ -93,121 +31,6 @@
struct lmb lmb;
-static void security_init(void)
-{
- /* Disable the backup domain write protection */
- /* the protection is enable at each reset by hardware */
- /* And must be disable by software */
- setbits_le32(PWR_CR1, PWR_CR1_DBP);
-
- while (!(readl(PWR_CR1) & PWR_CR1_DBP))
- ;
-
- /* If RTC clock isn't enable so this is a cold boot then we need
- * to reset the backup domain
- */
- if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
- setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
- while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
- ;
- clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
- }
-
- /* allow non secure access in Write/Read for all peripheral */
- writel(GENMASK(25, 0), ETZPC_DECPROT0);
-
- /* Open SYSRAM for no secure access */
- writel(0x0, ETZPC_TZMA1_SIZE);
-
- /* enable TZC1 TZC2 clock */
- writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
-
- /* Region 0 set to no access by default */
- /* bit 0 / 16 => nsaid0 read/write Enable
- * bit 1 / 17 => nsaid1 read/write Enable
- * ...
- * bit 15 / 31 => nsaid15 read/write Enable
- */
- writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
- /* bit 30 / 31 => Secure Global Enable : write/read */
- /* bit 0 / 1 => Region Enable for filter 0/1 */
- writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
-
- /* Enable Filter 0 and 1 */
- setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
-
- /* RCC trust zone deactivated */
- writel(0x0, RCC_TZCR);
-
- /* TAMP: deactivate the internal tamper
- * Bit 23 ITAMP8E: monotonic counter overflow
- * Bit 20 ITAMP5E: RTC calendar overflow
- * Bit 19 ITAMP4E: HSE monitoring
- * Bit 18 ITAMP3E: LSE monitoring
- * Bit 16 ITAMP1E: RTC power domain supply monitoring
- */
- writel(0x0, TAMP_CR1);
-
- /* GPIOZ: deactivate the security */
- writel(BIT(0), RCC_MP_AHB5ENSETR);
- writel(0x0, GPIOZ_SECCFGR);
-}
-
-/*
- * Debug init
- */
-static void dbgmcu_init(void)
-{
- /*
- * Freeze IWDG2 if Cortex-A7 is in debug mode
- * done in TF-A for TRUSTED boot and
- * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
- */
- if (bsec_dbgswenable()) {
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
- setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
- }
-}
-
-void spl_board_init(void)
-{
- struct udevice *dev;
- int ret;
-
- dbgmcu_init();
-
- /* force probe of BSEC driver to shadow the upper OTP */
- ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
- if (ret)
- log_warning("BSEC probe failed: %d\n", ret);
-}
-
-/* get bootmode from ROM code boot context: saved in TAMP register */
-static void update_bootmode(void)
-{
- u32 boot_mode;
- u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
- u32 bootrom_device, bootrom_instance;
-
- /* enable TAMP clock = RTCAPBEN */
- writel(BIT(8), RCC_MP_APB5ENSETR);
-
- /* read bootrom context */
- bootrom_device =
- (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
- bootrom_instance =
- (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
- boot_mode =
- ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
- ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
- BOOT_INSTANCE_MASK);
-
- /* save the boot mode in TAMP backup register */
- clrsetbits_le32(TAMP_BOOT_CONTEXT,
- TAMP_BOOT_MODE_MASK,
- boot_mode << TAMP_BOOT_MODE_SHIFT);
-}
-
u32 get_bootmode(void)
{
/* read bootmode from TAMP backup register */
@@ -229,8 +52,11 @@
enum dcache_option option;
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+/* STM32_SYSRAM_BASE exist only when SPL is supported */
+#ifdef CONFIG_SPL
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
+#endif
} else if (gd->flags & GD_FLG_RELOC) {
/* bd->bi_dram is available only after relocation */
start = bd->bi_dram[bank].start;
@@ -277,25 +103,24 @@
*/
int arch_cpu_init(void)
{
- u32 boot_mode;
-
early_enable_caches();
/* early armv7 timer init: needed for polling */
timer_init();
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
- security_init();
- update_bootmode();
- }
-/* reset copro state in SPL, when used, or in U-Boot */
- if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
- /* Reset Coprocessor state unless it wakes up from Standby power mode */
- if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
- writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
- writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
- }
- }
+ return 0;
+}
+
+/* weak function for SOC specific initialization */
+__weak void stm32mp_cpu_init(void)
+{
+}
+
+int mach_cpu_init(void)
+{
+ u32 boot_mode;
+
+ stm32mp_cpu_init();
boot_mode = get_bootmode();
@@ -324,139 +149,6 @@
dcache_enable();
}
-static u32 read_idc(void)
-{
- /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
- if (bsec_dbgswenable()) {
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
-
- return readl(DBGMCU_IDC);
- }
-
- if (CONFIG_IS_ENABLED(STM32MP15x))
- return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
- else
- return 0x0;
-}
-
-u32 get_cpu_dev(void)
-{
- return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
-}
-
-u32 get_cpu_rev(void)
-{
- return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
-}
-
-static u32 get_otp(int index, int shift, int mask)
-{
- int ret;
- struct udevice *dev;
- u32 otp = 0;
-
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_DRIVER_GET(stm32mp_bsec),
- &dev);
-
- if (!ret)
- ret = misc_read(dev, STM32_BSEC_SHADOW(index),
- &otp, sizeof(otp));
-
- return (otp >> shift) & mask;
-}
-
-/* Get Device Part Number (RPN) from OTP */
-static u32 get_cpu_rpn(void)
-{
- return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
-}
-
-u32 get_cpu_type(void)
-{
- return (get_cpu_dev() << 16) | get_cpu_rpn();
-}
-
-/* Get Package options from OTP */
-u32 get_cpu_package(void)
-{
- return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
-}
-
-static const char * const soc_type[] = {
- "????",
- "151C", "151A", "151F", "151D",
- "153C", "153A", "153F", "153D",
- "157C", "157A", "157F", "157D"
-};
-
-static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
-static const char * const soc_rev[] = { "?", "A", "B", "Z" };
-
-static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
- unsigned int *rev)
-{
- u32 cpu_type = get_cpu_type();
- u32 ct = cpu_type & ~(BIT(7) | BIT(0));
- u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
- u32 cp = get_cpu_package();
-
- /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
- switch (ct) {
- case CPU_STM32MP151Cxx:
- *type = cm + 1;
- break;
- case CPU_STM32MP153Cxx:
- *type = cm + 5;
- break;
- case CPU_STM32MP157Cxx:
- *type = cm + 9;
- break;
- default:
- *type = 0;
- break;
- }
-
- /* Package */
- switch (cp) {
- case PKG_AA_LBGA448:
- case PKG_AB_LBGA354:
- case PKG_AC_TFBGA361:
- case PKG_AD_TFBGA257:
- *pkg = cp;
- break;
- default:
- *pkg = 0;
- break;
- }
-
- /* Revision */
- switch (get_cpu_rev()) {
- case CPU_REV1:
- *rev = 1;
- break;
- case CPU_REV2:
- *rev = 2;
- break;
- case CPU_REV2_1:
- *rev = 3;
- break;
- default:
- *rev = 0;
- break;
- }
-}
-
-void get_soc_name(char name[SOC_NAME_SIZE])
-{
- unsigned int type, pkg, rev;
-
- get_cpu_string_offsets(&type, &pkg, &rev);
-
- snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
- soc_type[type], soc_pkg[pkg], soc_rev[rev]);
-}
-
/* used when CONFIG_DISPLAY_CPUINFO is activated */
int print_cpuinfo(void)
{
@@ -598,16 +290,18 @@
{
int ret;
int i;
- u32 otp[2];
+ u32 otp[3];
uchar enetaddr[6];
struct udevice *dev;
+ int nb_eth, nb_otp, index;
if (!IS_ENABLED(CONFIG_NET))
return 0;
- /* MAC already in environment */
- if (eth_env_get_enetaddr("ethaddr", enetaddr))
- return 0;
+ nb_eth = get_eth_nb();
+
+ /* 6 bytes for each MAC addr and 4 bytes for each OTP */
+ nb_otp = DIV_ROUND_UP(6 * nb_eth, 4);
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stm32mp_bsec),
@@ -615,22 +309,31 @@
if (ret)
return ret;
- ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
- otp, sizeof(otp));
+ ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp);
if (ret < 0)
return ret;
- for (i = 0; i < 6; i++)
- enetaddr[i] = ((uint8_t *)&otp)[i];
+ for (index = 0; index < nb_eth; index++) {
+ /* MAC already in environment */
+ if (eth_env_get_enetaddr_by_index("eth", index, enetaddr))
+ continue;
- if (!is_valid_ethaddr(enetaddr)) {
- log_err("invalid MAC address in OTP %pM\n", enetaddr);
- return -EINVAL;
+ for (i = 0; i < 6; i++)
+ enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index];
+
+ if (!is_valid_ethaddr(enetaddr)) {
+ log_err("invalid MAC address %d in OTP %pM\n",
+ index, enetaddr);
+ return -EINVAL;
+ }
+ log_debug("OTP MAC address %d = %pM\n", index, enetaddr);
+ ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr);
+ if (ret) {
+ log_err("Failed to set mac address %pM from OTP: %d\n",
+ enetaddr, ret);
+ return ret;
+ }
}
- log_debug("OTP MAC address = %pM\n", enetaddr);
- ret = eth_env_set_enetaddr("ethaddr", enetaddr);
- if (ret)
- log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
return 0;
}
@@ -662,15 +365,8 @@
return 0;
}
-static void setup_soc_type_pkg_rev(void)
+__weak void stm32mp_misc_init(void)
{
- unsigned int type, pkg, rev;
-
- get_cpu_string_offsets(&type, &pkg, &rev);
-
- env_set("soc_type", soc_type[type]);
- env_set("soc_pkg", soc_pkg[pkg]);
- env_set("soc_rev", soc_rev[rev]);
}
int arch_misc_init(void)
@@ -678,7 +374,7 @@
setup_boot_mode();
setup_mac_address();
setup_serial_number();
- setup_soc_type_pkg_rev();
+ stm32mp_misc_init();
return 0;
}
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
index b1a4b76..3b4c05d 100644
--- a/arch/arm/mach-stm32mp/fdt.c
+++ b/arch/arm/mach-stm32mp/fdt.c
@@ -28,13 +28,120 @@
#define ETZPC_RESERVED 0xffffffff
-#define STM32_FDCAN_BASE 0x4400e000
-#define STM32_CRYP2_BASE 0x4c005000
-#define STM32_CRYP1_BASE 0x54001000
-#define STM32_GPU_BASE 0x59000000
-#define STM32_DSI_BASE 0x5a000000
+#define STM32MP13_FDCAN_BASE 0x4400F000
+#define STM32MP13_ADC1_BASE 0x48003000
+#define STM32MP13_TSC_BASE 0x5000B000
+#define STM32MP13_CRYP_BASE 0x54002000
+#define STM32MP13_ETH2_BASE 0x5800E000
+#define STM32MP13_DCMIPP_BASE 0x5A000000
+#define STM32MP13_LTDC_BASE 0x5A010000
-static const u32 stm32mp1_ip_addr[] = {
+#define STM32MP15_FDCAN_BASE 0x4400e000
+#define STM32MP15_CRYP2_BASE 0x4c005000
+#define STM32MP15_CRYP1_BASE 0x54001000
+#define STM32MP15_GPU_BASE 0x59000000
+#define STM32MP15_DSI_BASE 0x5a000000
+
+static const u32 stm32mp13_ip_addr[] = {
+ 0x50025000, /* 0 VREFBUF APB3 */
+ 0x50021000, /* 1 LPTIM2 APB3 */
+ 0x50022000, /* 2 LPTIM3 APB3 */
+ STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
+ STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
+ 0x5A006000, /* 5 USBPHYCTRL APB4 */
+ 0x5A003000, /* 6 DDRCTRLPHY APB4 */
+ ETZPC_RESERVED, /* 7 Reserved*/
+ ETZPC_RESERVED, /* 8 Reserved*/
+ ETZPC_RESERVED, /* 9 Reserved*/
+ 0x5C006000, /* 10 TZC APB5 */
+ 0x58001000, /* 11 MCE APB5 */
+ 0x5C000000, /* 12 IWDG1 APB5 */
+ 0x5C008000, /* 13 STGENC APB5 */
+ ETZPC_RESERVED, /* 14 Reserved*/
+ ETZPC_RESERVED, /* 15 Reserved*/
+ 0x4C000000, /* 16 USART1 APB6 */
+ 0x4C001000, /* 17 USART2 APB6 */
+ 0x4C002000, /* 18 SPI4 APB6 */
+ 0x4C003000, /* 19 SPI5 APB6 */
+ 0x4C004000, /* 20 I2C3 APB6 */
+ 0x4C005000, /* 21 I2C4 APB6 */
+ 0x4C006000, /* 22 I2C5 APB6 */
+ 0x4C007000, /* 23 TIM12 APB6 */
+ 0x4C008000, /* 24 TIM13 APB6 */
+ 0x4C009000, /* 25 TIM14 APB6 */
+ 0x4C00A000, /* 26 TIM15 APB6 */
+ 0x4C00B000, /* 27 TIM16 APB6 */
+ 0x4C00C000, /* 28 TIM17 APB6 */
+ ETZPC_RESERVED, /* 29 Reserved*/
+ ETZPC_RESERVED, /* 30 Reserved*/
+ ETZPC_RESERVED, /* 31 Reserved*/
+ STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
+ 0x48004000, /* 33 ADC2 AHB2 */
+ 0x49000000, /* 34 OTG AHB2 */
+ ETZPC_RESERVED, /* 35 Reserved*/
+ ETZPC_RESERVED, /* 36 Reserved*/
+ STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
+ ETZPC_RESERVED, /* 38 Reserved*/
+ ETZPC_RESERVED, /* 39 Reserved*/
+ 0x54004000, /* 40 RNG AHB5 */
+ 0x54003000, /* 41 HASH AHB5 */
+ STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
+ 0x54005000, /* 43 SAES AHB5 */
+ 0x54006000, /* 44 PKA AHB5 */
+ 0x54000000, /* 45 BKPSRAM AHB5 */
+ ETZPC_RESERVED, /* 46 Reserved*/
+ ETZPC_RESERVED, /* 47 Reserved*/
+ 0x5800A000, /* 48 ETH1 AHB6 */
+ STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
+ 0x58005000, /* 50 SDMMC1 AHB6 */
+ 0x58007000, /* 51 SDMMC2 AHB6 */
+ ETZPC_RESERVED, /* 52 Reserved*/
+ ETZPC_RESERVED, /* 53 Reserved*/
+ 0x58002000, /* 54 FMC AHB6 */
+ 0x58003000, /* 55 QSPI AHB6 */
+ ETZPC_RESERVED, /* 56 Reserved*/
+ ETZPC_RESERVED, /* 57 Reserved*/
+ ETZPC_RESERVED, /* 58 Reserved*/
+ ETZPC_RESERVED, /* 59 Reserved*/
+ 0x30000000, /* 60 SRAM1 MLAHB */
+ 0x30004000, /* 61 SRAM2 MLAHB */
+ 0x30006000, /* 62 SRAM3 MLAHB */
+ ETZPC_RESERVED, /* 63 Reserved*/
+ ETZPC_RESERVED, /* 64 Reserved*/
+ ETZPC_RESERVED, /* 65 Reserved*/
+ ETZPC_RESERVED, /* 66 Reserved*/
+ ETZPC_RESERVED, /* 67 Reserved*/
+ ETZPC_RESERVED, /* 68 Reserved*/
+ ETZPC_RESERVED, /* 69 Reserved*/
+ ETZPC_RESERVED, /* 70 Reserved*/
+ ETZPC_RESERVED, /* 71 Reserved*/
+ ETZPC_RESERVED, /* 72 Reserved*/
+ ETZPC_RESERVED, /* 73 Reserved*/
+ ETZPC_RESERVED, /* 74 Reserved*/
+ ETZPC_RESERVED, /* 75 Reserved*/
+ ETZPC_RESERVED, /* 76 Reserved*/
+ ETZPC_RESERVED, /* 77 Reserved*/
+ ETZPC_RESERVED, /* 78 Reserved*/
+ ETZPC_RESERVED, /* 79 Reserved*/
+ ETZPC_RESERVED, /* 80 Reserved*/
+ ETZPC_RESERVED, /* 81 Reserved*/
+ ETZPC_RESERVED, /* 82 Reserved*/
+ ETZPC_RESERVED, /* 83 Reserved*/
+ ETZPC_RESERVED, /* 84 Reserved*/
+ ETZPC_RESERVED, /* 85 Reserved*/
+ ETZPC_RESERVED, /* 86 Reserved*/
+ ETZPC_RESERVED, /* 87 Reserved*/
+ ETZPC_RESERVED, /* 88 Reserved*/
+ ETZPC_RESERVED, /* 89 Reserved*/
+ ETZPC_RESERVED, /* 90 Reserved*/
+ ETZPC_RESERVED, /* 91 Reserved*/
+ ETZPC_RESERVED, /* 92 Reserved*/
+ ETZPC_RESERVED, /* 93 Reserved*/
+ ETZPC_RESERVED, /* 94 Reserved*/
+ ETZPC_RESERVED, /* 95 Reserved*/
+};
+
+static const u32 stm32mp15_ip_addr[] = {
0x5c008000, /* 00 stgenc */
0x54000000, /* 01 bkpsram */
0x5c003000, /* 02 iwdg1 */
@@ -44,7 +151,7 @@
ETZPC_RESERVED, /* 06 reserved */
0x54003000, /* 07 rng1 */
0x54002000, /* 08 hash1 */
- STM32_CRYP1_BASE, /* 09 cryp1 */
+ STM32MP15_CRYP1_BASE, /* 09 cryp1 */
0x5a003000, /* 0A ddrctrl */
0x5a004000, /* 0B ddrphyc */
0x5c009000, /* 0C i2c6 */
@@ -97,7 +204,7 @@
0x4400b000, /* 3B sai2 */
0x4400c000, /* 3C sai3 */
0x4400d000, /* 3D dfsdm */
- STM32_FDCAN_BASE, /* 3E tt_fdcan */
+ STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
ETZPC_RESERVED, /* 3F reserved */
0x50021000, /* 40 lptim2 */
0x50022000, /* 41 lptim3 */
@@ -110,7 +217,7 @@
0x48003000, /* 48 adc */
0x4c002000, /* 49 hash2 */
0x4c003000, /* 4A rng2 */
- STM32_CRYP2_BASE, /* 4B cryp2 */
+ STM32MP15_CRYP2_BASE, /* 4B cryp2 */
ETZPC_RESERVED, /* 4C reserved */
ETZPC_RESERVED, /* 4D reserved */
ETZPC_RESERVED, /* 4E reserved */
@@ -163,8 +270,15 @@
int offset, shift;
u32 addr, status, decprot[ETZPC_DECPROT_NB];
- array = stm32mp1_ip_addr;
- array_size = ARRAY_SIZE(stm32mp1_ip_addr);
+ if (IS_ENABLED(CONFIG_STM32MP13x)) {
+ array = stm32mp13_ip_addr;
+ array_size = ARRAY_SIZE(stm32mp13_ip_addr);
+ }
+
+ if (IS_ENABLED(CONFIG_STM32MP15x)) {
+ array = stm32mp15_ip_addr;
+ array_size = ARRAY_SIZE(stm32mp15_ip_addr);
+ }
for (i = 0; i < ETZPC_DECPROT_NB; i++)
decprot[i] = readl(ETZPC_DECPROT(i));
@@ -248,6 +362,107 @@
}
}
+static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
+{
+ switch (cpu) {
+ case CPU_STM32MP131Fxx:
+ case CPU_STM32MP131Dxx:
+ case CPU_STM32MP131Cxx:
+ case CPU_STM32MP131Axx:
+ stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name);
+ stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name);
+ fallthrough;
+ case CPU_STM32MP133Fxx:
+ case CPU_STM32MP133Dxx:
+ case CPU_STM32MP133Cxx:
+ case CPU_STM32MP133Axx:
+ stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name);
+ stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp",
+ name);
+ stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name);
+ break;
+ default:
+ break;
+ }
+
+ switch (cpu) {
+ case CPU_STM32MP135Dxx:
+ case CPU_STM32MP135Axx:
+ case CPU_STM32MP133Dxx:
+ case CPU_STM32MP133Axx:
+ case CPU_STM32MP131Dxx:
+ case CPU_STM32MP131Axx:
+ stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name);
+ break;
+ default:
+ break;
+ }
+}
+
+static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
+{
+ u32 pkg;
+
+ switch (cpu) {
+ case CPU_STM32MP151Fxx:
+ case CPU_STM32MP151Dxx:
+ case CPU_STM32MP151Cxx:
+ case CPU_STM32MP151Axx:
+ stm32_fdt_fixup_cpu(blob, name);
+ /* after cpu delete we can't trust the soc offsets anymore */
+ soc = fdt_path_offset(blob, "/soc");
+ stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
+ fallthrough;
+ case CPU_STM32MP153Fxx:
+ case CPU_STM32MP153Dxx:
+ case CPU_STM32MP153Cxx:
+ case CPU_STM32MP153Axx:
+ stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
+ stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
+ break;
+ default:
+ break;
+ }
+ switch (cpu) {
+ case CPU_STM32MP157Dxx:
+ case CPU_STM32MP157Axx:
+ case CPU_STM32MP153Dxx:
+ case CPU_STM32MP153Axx:
+ case CPU_STM32MP151Dxx:
+ case CPU_STM32MP151Axx:
+ stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp",
+ name);
+ stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp",
+ name);
+ break;
+ default:
+ break;
+ }
+ switch (get_cpu_package()) {
+ case STM32MP15_PKG_AA_LBGA448:
+ pkg = STM32MP_PKG_AA;
+ break;
+ case STM32MP15_PKG_AB_LBGA354:
+ pkg = STM32MP_PKG_AB;
+ break;
+ case STM32MP15_PKG_AC_TFBGA361:
+ pkg = STM32MP_PKG_AC;
+ break;
+ case STM32MP15_PKG_AD_TFBGA257:
+ pkg = STM32MP_PKG_AD;
+ break;
+ default:
+ pkg = 0;
+ break;
+ }
+ if (pkg) {
+ do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
+ "st,package", pkg, false);
+ do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
+ "st,package", pkg, false);
+ }
+}
+
/*
* This function is called right before the kernel is booted. "blob" is the
* device tree that will be passed to the kernel.
@@ -256,7 +471,7 @@
{
int ret = 0;
int soc;
- u32 pkg, cpu;
+ u32 cpu;
char name[SOC_NAME_SIZE];
soc = fdt_path_offset(blob, "/soc");
@@ -276,76 +491,24 @@
cpu = get_cpu_type();
get_soc_name(name);
- switch (cpu) {
- case CPU_STM32MP151Fxx:
- case CPU_STM32MP151Dxx:
- case CPU_STM32MP151Cxx:
- case CPU_STM32MP151Axx:
- stm32_fdt_fixup_cpu(blob, name);
- /* after cpu delete we can't trust the soc offsets anymore */
- soc = fdt_path_offset(blob, "/soc");
- stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
- /* fall through */
- case CPU_STM32MP153Fxx:
- case CPU_STM32MP153Dxx:
- case CPU_STM32MP153Cxx:
- case CPU_STM32MP153Axx:
- stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
- stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
- break;
- default:
- break;
- }
+ if (IS_ENABLED(CONFIG_STM32MP13x))
+ stm32mp13_fdt_fixup(blob, soc, cpu, name);
- switch (cpu) {
- case CPU_STM32MP157Dxx:
- case CPU_STM32MP157Axx:
- case CPU_STM32MP153Dxx:
- case CPU_STM32MP153Axx:
- case CPU_STM32MP151Dxx:
- case CPU_STM32MP151Axx:
- stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
- stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
- break;
- default:
- break;
- }
+ if (IS_ENABLED(CONFIG_STM32MP15x)) {
+ stm32mp15_fdt_fixup(blob, soc, cpu, name);
- switch (get_cpu_package()) {
- case PKG_AA_LBGA448:
- pkg = STM32MP_PKG_AA;
- break;
- case PKG_AB_LBGA354:
- pkg = STM32MP_PKG_AB;
- break;
- case PKG_AC_TFBGA361:
- pkg = STM32MP_PKG_AC;
- break;
- case PKG_AD_TFBGA257:
- pkg = STM32MP_PKG_AD;
- break;
- default:
- pkg = 0;
- break;
+ /*
+ * TEMP: remove OP-TEE nodes in kernel device tree
+ * copied from U-Boot device tree by optee_copy_fdt_nodes
+ * when OP-TEE is not detected (probe failed)
+ * these OP-TEE nodes are present in <board>-u-boot.dtsi
+ * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
+ * when FIP is not used by TF-A
+ */
+ if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
+ !tee_find_device(NULL, NULL, NULL, NULL))
+ stm32_fdt_disable_optee(blob);
}
- if (pkg) {
- do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
- "st,package", pkg, false);
- do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
- "st,package", pkg, false);
- }
-
- /*
- * TEMP: remove OP-TEE nodes in kernel device tree
- * copied from U-Boot device tree by optee_copy_fdt_nodes
- * when OP-TEE is not detected (probe failed)
- * these OP-TEE nodes are present in <board>-u-boot.dtsi
- * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
- * when FIP is not used by TF-A
- */
- if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
- !tee_find_device(NULL, NULL, NULL, NULL))
- stm32_fdt_disable_optee(blob);
return ret;
}
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 47e88fc..c70375a 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -17,7 +17,9 @@
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
#define STM32_SYSCFG_BASE 0x50020000
+#ifdef CONFIG_STM32MP15x
#define STM32_DBGMCU_BASE 0x50081000
+#endif
#define STM32_FMC2_BASE 0x58002000
#define STM32_DDRCTRL_BASE 0x5A003000
#define STM32_DDRPHYC_BASE 0x5A004000
@@ -26,8 +28,14 @@
#define STM32_STGEN_BASE 0x5C008000
#define STM32_TAMP_BASE 0x5C00A000
+#ifdef CONFIG_STM32MP15x
#define STM32_USART1_BASE 0x5C000000
#define STM32_USART2_BASE 0x4000E000
+#endif
+#ifdef CONFIG_STM32MP13x
+#define STM32_USART1_BASE 0x4c000000
+#define STM32_USART2_BASE 0x4c001000
+#endif
#define STM32_USART3_BASE 0x4000F000
#define STM32_UART4_BASE 0x40010000
#define STM32_UART5_BASE 0x40011000
@@ -39,8 +47,10 @@
#define STM32_SDMMC2_BASE 0x58007000
#define STM32_SDMMC3_BASE 0x48004000
+#ifdef CONFIG_STM32MP15x
#define STM32_SYSRAM_BASE 0x2FFC0000
#define STM32_SYSRAM_SIZE SZ_256K
+#endif
#define STM32_DDR_BASE 0xC0000000
#define STM32_DDR_SIZE SZ_1G
@@ -98,6 +108,8 @@
/* TAMP registers */
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
+
+#ifdef CONFIG_STM32MP15x
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17)
@@ -111,13 +123,18 @@
#define TAMP_COPRO_STATE_CSTOP 3
#define TAMP_COPRO_STATE_STANDBY 4
#define TAMP_COPRO_STATE_CRASH 5
+#endif
+
+#ifdef CONFIG_STM32MP13x
+#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31)
+#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
+#endif
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_SHIFT 8
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
-#define TAMP_BOOT_DEBUG_ON BIT(16)
enum forced_boot_mode {
BOOT_NORMAL = 0x00,
@@ -138,11 +155,19 @@
#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
/* BSEC OTP index */
+#ifdef CONFIG_STM32MP15x
#define BSEC_OTP_RPN 1
#define BSEC_OTP_SERIAL 13
#define BSEC_OTP_PKG 16
#define BSEC_OTP_MAC 57
#define BSEC_OTP_BOARD 59
+#endif
+#ifdef CONFIG_STM32MP13x
+#define BSEC_OTP_RPN 1
+#define BSEC_OTP_SERIAL 13
+#define BSEC_OTP_MAC 57
+#define BSEC_OTP_BOARD 60
+#endif
#endif /* __ASSEMBLY__ */
#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index b91f98e..4b564e8 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -3,7 +3,7 @@
* Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
*/
-/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */
+/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
#define CPU_STM32MP157Cxx 0x05000000
#define CPU_STM32MP157Axx 0x05000001
#define CPU_STM32MP153Cxx 0x05000024
@@ -17,10 +17,24 @@
#define CPU_STM32MP151Fxx 0x050000AE
#define CPU_STM32MP151Dxx 0x050000AF
+#define CPU_STM32MP135Cxx 0x05010000
+#define CPU_STM32MP135Axx 0x05010001
+#define CPU_STM32MP133Cxx 0x050100C0
+#define CPU_STM32MP133Axx 0x050100C1
+#define CPU_STM32MP131Cxx 0x050106C8
+#define CPU_STM32MP131Axx 0x050106C9
+#define CPU_STM32MP135Fxx 0x05010800
+#define CPU_STM32MP135Dxx 0x05010801
+#define CPU_STM32MP133Fxx 0x050108C0
+#define CPU_STM32MP133Dxx 0x050108C1
+#define CPU_STM32MP131Fxx 0x05010EC8
+#define CPU_STM32MP131Dxx 0x05010EC9
+
/* return CPU_STMP32MP...Xxx constants */
u32 get_cpu_type(void);
#define CPU_DEV_STM32MP15 0x500
+#define CPU_DEV_STM32MP13 0x501
/* return CPU_DEV constants */
u32 get_cpu_dev(void);
@@ -36,10 +50,12 @@
/* Get Package options from OTP */
u32 get_cpu_package(void);
-#define PKG_AA_LBGA448 4
-#define PKG_AB_LBGA354 3
-#define PKG_AC_TFBGA361 2
-#define PKG_AD_TFBGA257 1
+/* package used for STM32MP15x */
+#define STM32MP15_PKG_AA_LBGA448 4
+#define STM32MP15_PKG_AB_LBGA354 3
+#define STM32MP15_PKG_AC_TFBGA361 2
+#define STM32MP15_PKG_AD_TFBGA257 1
+#define STM32MP15_PKG_UNKNOWN 0
/* Get SOC name */
#define SOC_NAME_SIZE 20
@@ -48,7 +64,15 @@
/* return boot mode */
u32 get_bootmode(void);
+int get_eth_nb(void);
int setup_mac_address(void);
/* board power management : configure vddcore according OPP */
void board_vddcore_init(u32 voltage_mv);
+
+/* weak function */
+void stm32mp_cpu_init(void);
+void stm32mp_misc_init(void);
+
+/* helper function: read data from OTP */
+u32 get_otp(int index, int shift, int mask);
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index 78fa9d7..19d9fe0 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -190,6 +190,7 @@
int ret;
arch_cpu_init();
+ mach_cpu_init();
ret = spl_early_init();
if (ret) {
diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp13x.c
new file mode 100644
index 0000000..bd3f24c
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp13x.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <common.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+
+/* SYSCFG register */
+#define SYSCFG_IDC_OFFSET 0x380
+#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
+#define SYSCFG_IDC_DEV_ID_SHIFT 0
+#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
+#define SYSCFG_IDC_REV_ID_SHIFT 16
+
+/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */
+#define RPN_SHIFT 0
+#define RPN_MASK GENMASK(11, 0)
+
+static u32 read_idc(void)
+{
+ void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ return readl(syscfg + SYSCFG_IDC_OFFSET);
+}
+
+u32 get_cpu_dev(void)
+{
+ return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT;
+}
+
+u32 get_cpu_rev(void)
+{
+ return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
+}
+
+/* Get Device Part Number (RPN) from OTP */
+static u32 get_cpu_rpn(void)
+{
+ return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+}
+
+u32 get_cpu_type(void)
+{
+ return (get_cpu_dev() << 16) | get_cpu_rpn();
+}
+
+int get_eth_nb(void)
+{
+ int nb_eth = 2;
+
+ switch (get_cpu_type()) {
+ case CPU_STM32MP131Dxx:
+ fallthrough;
+ case CPU_STM32MP131Cxx:
+ fallthrough;
+ case CPU_STM32MP131Axx:
+ nb_eth = 1;
+ break;
+ default:
+ nb_eth = 2;
+ break;
+ }
+
+ return nb_eth;
+}
+
+void get_soc_name(char name[SOC_NAME_SIZE])
+{
+ char *cpu_s, *cpu_r;
+
+ /* MPUs Part Numbers */
+ switch (get_cpu_type()) {
+ case CPU_STM32MP135Fxx:
+ cpu_s = "135F";
+ break;
+ case CPU_STM32MP135Dxx:
+ cpu_s = "135D";
+ break;
+ case CPU_STM32MP135Cxx:
+ cpu_s = "135C";
+ break;
+ case CPU_STM32MP135Axx:
+ cpu_s = "135A";
+ break;
+ case CPU_STM32MP133Fxx:
+ cpu_s = "133F";
+ break;
+ case CPU_STM32MP133Dxx:
+ cpu_s = "133D";
+ break;
+ case CPU_STM32MP133Cxx:
+ cpu_s = "133C";
+ break;
+ case CPU_STM32MP133Axx:
+ cpu_s = "133A";
+ break;
+ case CPU_STM32MP131Fxx:
+ cpu_s = "131F";
+ break;
+ case CPU_STM32MP131Dxx:
+ cpu_s = "131D";
+ break;
+ case CPU_STM32MP131Cxx:
+ cpu_s = "131C";
+ break;
+ case CPU_STM32MP131Axx:
+ cpu_s = "131A";
+ break;
+ default:
+ cpu_s = "????";
+ break;
+ }
+
+ /* REVISION */
+ switch (get_cpu_rev()) {
+ case CPU_REV1:
+ cpu_r = "A";
+ break;
+ case CPU_REV1_1:
+ cpu_r = "Z";
+ break;
+ default:
+ cpu_r = "?";
+ break;
+ }
+
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r);
+}
diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c
new file mode 100644
index 0000000..a093e61
--- /dev/null
+++ b/arch/arm/mach-stm32mp/stm32mp15x.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <common.h>
+#include <env.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/bsec.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+/* RCC register */
+#define RCC_TZCR (STM32_RCC_BASE + 0x00)
+#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
+#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
+#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
+#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
+
+#define RCC_BDCR_VSWRST BIT(31)
+#define RCC_BDCR_RTCSRC GENMASK(17, 16)
+
+#define RCC_DBGCFGR_DBGCKEN BIT(8)
+
+/* DBGMCU register */
+#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
+#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
+#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
+
+/* Security register */
+#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
+#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
+
+#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
+#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
+#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
+
+#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
+
+#define PWR_CR1 (STM32_PWR_BASE + 0x00)
+#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
+#define PWR_CR1_DBP BIT(8)
+#define PWR_MCUCR_SBF BIT(6)
+
+/* GPIOZ registers */
+#define GPIOZ_SECCFGR 0x54004030
+
+/* DBGMCU register */
+#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
+#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
+#define DBGMCU_IDC_DEV_ID_SHIFT 0
+#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
+#define DBGMCU_IDC_REV_ID_SHIFT 16
+
+/* boot interface from Bootrom
+ * - boot instance = bit 31:16
+ * - boot device = bit 15:0
+ */
+#define BOOTROM_PARAM_ADDR 0x2FFC0078
+#define BOOTROM_MODE_MASK GENMASK(15, 0)
+#define BOOTROM_MODE_SHIFT 0
+#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
+#define BOOTROM_INSTANCE_SHIFT 16
+
+/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
+#define RPN_SHIFT 0
+#define RPN_MASK GENMASK(7, 0)
+
+/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines
+ * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
+ * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
+ * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
+ * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
+ * - others: Reserved
+ */
+#define PKG_SHIFT 27
+#define PKG_MASK GENMASK(2, 0)
+
+static void security_init(void)
+{
+ /* Disable the backup domain write protection */
+ /* the protection is enable at each reset by hardware */
+ /* And must be disable by software */
+ setbits_le32(PWR_CR1, PWR_CR1_DBP);
+
+ while (!(readl(PWR_CR1) & PWR_CR1_DBP))
+ ;
+
+ /* If RTC clock isn't enable so this is a cold boot then we need
+ * to reset the backup domain
+ */
+ if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
+ setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
+ ;
+ clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ }
+
+ /* allow non secure access in Write/Read for all peripheral */
+ writel(GENMASK(25, 0), ETZPC_DECPROT0);
+
+ /* Open SYSRAM for no secure access */
+ writel(0x0, ETZPC_TZMA1_SIZE);
+
+ /* enable TZC1 TZC2 clock */
+ writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
+
+ /* Region 0 set to no access by default */
+ /* bit 0 / 16 => nsaid0 read/write Enable
+ * bit 1 / 17 => nsaid1 read/write Enable
+ * ...
+ * bit 15 / 31 => nsaid15 read/write Enable
+ */
+ writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
+ /* bit 30 / 31 => Secure Global Enable : write/read */
+ /* bit 0 / 1 => Region Enable for filter 0/1 */
+ writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
+
+ /* Enable Filter 0 and 1 */
+ setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
+
+ /* RCC trust zone deactivated */
+ writel(0x0, RCC_TZCR);
+
+ /* TAMP: deactivate the internal tamper
+ * Bit 23 ITAMP8E: monotonic counter overflow
+ * Bit 20 ITAMP5E: RTC calendar overflow
+ * Bit 19 ITAMP4E: HSE monitoring
+ * Bit 18 ITAMP3E: LSE monitoring
+ * Bit 16 ITAMP1E: RTC power domain supply monitoring
+ */
+ writel(0x0, TAMP_CR1);
+
+ /* GPIOZ: deactivate the security */
+ writel(BIT(0), RCC_MP_AHB5ENSETR);
+ writel(0x0, GPIOZ_SECCFGR);
+}
+
+/*
+ * Debug init
+ */
+void dbgmcu_init(void)
+{
+ /*
+ * Freeze IWDG2 if Cortex-A7 is in debug mode
+ * done in TF-A for TRUSTED boot and
+ * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
+ */
+ if (bsec_dbgswenable()) {
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+ }
+}
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ dbgmcu_init();
+
+ /* force probe of BSEC driver to shadow the upper OTP */
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
+ if (ret)
+ log_warning("BSEC probe failed: %d\n", ret);
+}
+
+/* get bootmode from ROM code boot context: saved in TAMP register */
+static void update_bootmode(void)
+{
+ u32 boot_mode;
+ u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
+ u32 bootrom_device, bootrom_instance;
+
+ /* enable TAMP clock = RTCAPBEN */
+ writel(BIT(8), RCC_MP_APB5ENSETR);
+
+ /* read bootrom context */
+ bootrom_device =
+ (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
+ bootrom_instance =
+ (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
+ boot_mode =
+ ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
+ ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
+ BOOT_INSTANCE_MASK);
+
+ /* save the boot mode in TAMP backup register */
+ clrsetbits_le32(TAMP_BOOT_CONTEXT,
+ TAMP_BOOT_MODE_MASK,
+ boot_mode << TAMP_BOOT_MODE_SHIFT);
+}
+
+/* weak function: STM32MP15x mach init for boot without TFA */
+void stm32mp_cpu_init(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ security_init();
+ update_bootmode();
+ }
+
+ /* reset copro state in SPL, when used, or in U-Boot */
+ if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Reset Coprocessor state unless it wakes up from Standby power mode */
+ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
+ writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
+ writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
+ }
+ }
+}
+
+static u32 read_idc(void)
+{
+ /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
+ if (bsec_dbgswenable()) {
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+
+ return readl(DBGMCU_IDC);
+ }
+
+ return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
+}
+
+u32 get_cpu_dev(void)
+{
+ return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
+}
+
+u32 get_cpu_rev(void)
+{
+ return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
+}
+
+/* Get Device Part Number (RPN) from OTP */
+static u32 get_cpu_rpn(void)
+{
+ return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+}
+
+u32 get_cpu_type(void)
+{
+ return (get_cpu_dev() << 16) | get_cpu_rpn();
+}
+
+int get_eth_nb(void)
+{
+ return 1;
+}
+
+/* Get Package options from OTP */
+u32 get_cpu_package(void)
+{
+ return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
+}
+
+static const char * const soc_type[] = {
+ "????",
+ "151C", "151A", "151F", "151D",
+ "153C", "153A", "153F", "153D",
+ "157C", "157A", "157F", "157D"
+};
+
+static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
+static const char * const soc_rev[] = { "?", "A", "B", "Z" };
+
+static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
+ unsigned int *rev)
+{
+ u32 cpu_type = get_cpu_type();
+ u32 ct = cpu_type & ~(BIT(7) | BIT(0));
+ u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
+ u32 cp = get_cpu_package();
+
+ /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
+ switch (ct) {
+ case CPU_STM32MP151Cxx:
+ *type = cm + 1;
+ break;
+ case CPU_STM32MP153Cxx:
+ *type = cm + 5;
+ break;
+ case CPU_STM32MP157Cxx:
+ *type = cm + 9;
+ break;
+ default:
+ *type = 0;
+ break;
+ }
+
+ /* Package */
+ switch (cp) {
+ case STM32MP15_PKG_AA_LBGA448:
+ case STM32MP15_PKG_AB_LBGA354:
+ case STM32MP15_PKG_AC_TFBGA361:
+ case STM32MP15_PKG_AD_TFBGA257:
+ *pkg = cp;
+ break;
+ default:
+ *pkg = 0;
+ break;
+ }
+
+ /* Revision */
+ switch (get_cpu_rev()) {
+ case CPU_REV1:
+ *rev = 1;
+ break;
+ case CPU_REV2:
+ *rev = 2;
+ break;
+ case CPU_REV2_1:
+ *rev = 3;
+ break;
+ default:
+ *rev = 0;
+ break;
+ }
+}
+
+void get_soc_name(char name[SOC_NAME_SIZE])
+{
+ unsigned int type, pkg, rev;
+
+ get_cpu_string_offsets(&type, &pkg, &rev);
+
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
+ soc_type[type], soc_pkg[pkg], soc_rev[rev]);
+}
+
+static void setup_soc_type_pkg_rev(void)
+{
+ unsigned int type, pkg, rev;
+
+ get_cpu_string_offsets(&type, &pkg, &rev);
+
+ env_set("soc_type", soc_type[type]);
+ env_set("soc_pkg", soc_pkg[pkg]);
+ env_set("soc_rev", soc_rev[rev]);
+}
+
+/* weak function called in arch_misc_init */
+void stm32mp_misc_init(void)
+{
+ setup_soc_type_pkg_rev();
+}
diff --git a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
index 36db50f..6c722d0 100644
--- a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
@@ -6,8 +6,9 @@
#include <config.h>
#include <linux/linkage.h>
+#include <system-constants.h>
ENTRY(lowlevel_init)
- ldr sp, = CONFIG_SYS_INIT_SP_ADDR
+ ldr sp, = SYS_INIT_SP_ADDR
b uniphier_cache_disable
ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
index d116d46..1ba012c 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
@@ -18,7 +18,7 @@
static void _debug_uart_putc(int c)
{
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
;
@@ -57,7 +57,7 @@
void _debug_uart_init(void)
{
#ifdef CONFIG_SPL_BUILD
- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
unsigned int divisor;
switch (uniphier_get_soc_id()) {
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 7f6e431..e609ae0 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -53,12 +53,6 @@
select DM_SERIAL
bool
-config MCF5227x
- select OF_CONTROL
- select DM
- select DM_SERIAL
- bool
-
# processor type
config M5208
bool
diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile
deleted file mode 100644
index 6a38c48..0000000
--- a/arch/m68k/cpu/mcf5227x/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-# ccflags-y += -DET_DEBUG
-
-extra-y = start.o
-obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o
diff --git a/arch/m68k/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c
deleted file mode 100644
index a7adf64..0000000
--- a/arch/m68k/cpu/mcf5227x/cpu.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <vsprintf.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/immap.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- rcm_t *rcm = (rcm_t *) (MMAP_RCM);
- udelay(1000);
- setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
-
- /* we don't return! */
- return 0;
-};
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- ccm_t *ccm = (ccm_t *) MMAP_CCM;
- u16 msk;
- u16 id = 0;
- u8 ver;
-
- puts("CPU: ");
- msk = (in_be16(&ccm->cir) >> 6);
- ver = (in_be16(&ccm->cir) & 0x003f);
- switch (msk) {
- case 0x6c:
- id = 52277;
- break;
- }
-
- if (id) {
- char buf1[32], buf2[32], buf3[32];
-
- printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
- ver);
- printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
- strmhz(buf1, gd->cpu_clk),
- strmhz(buf2, gd->bus_clk),
- strmhz(buf3, gd->arch.flb_clk));
- printf(" INP CLK %s MHz VCO CLK %s MHz\n",
- strmhz(buf1, gd->arch.inp_clk),
- strmhz(buf2, gd->arch.vco_clk));
- }
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c
deleted file mode 100644
index 4ab13b4..0000000
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <watchdog.h>
-
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <asm/rtc.h>
-#include <linux/compiler.h>
-
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *)MMAP_GPIO;
-
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-}
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
-
-#if !defined(CONFIG_CF_SBF)
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- pll_t *pll = (pll_t *)MMAP_PLL;
-
- /* Workaround, must place before fbcs */
- out_be32(&pll->psr, 0x12);
-
- out_be32(&scm1->mpr, 0x77777777);
- out_be32(&scm1->pacra, 0);
- out_be32(&scm1->pacrb, 0);
- out_be32(&scm1->pacrc, 0);
- out_be32(&scm1->pacrd, 0);
- out_be32(&scm1->pacre, 0);
- out_be32(&scm1->pacrf, 0);
- out_be32(&scm1->pacrg, 0);
- out_be32(&scm1->pacri, 0);
-
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
-#endif
-#endif /* CONFIG_CF_SBF */
-
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
- && defined(CONFIG_SYS_CS4_CTRL))
- out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
- out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
- out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
- && defined(CONFIG_SYS_CS5_CTRL))
- out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
- out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
- out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
-#endif
-
-#ifdef CONFIG_SYS_I2C_FSL
- out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
-#endif
-
- icache_enable();
-
- cfspi_port_conf();
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
-#ifdef CONFIG_MCFRTC
- rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
- rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
-
- out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
- out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
-#endif
-
- return (0);
-}
-
-void uart_port_conf(int port)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Setup Ports: */
- switch (port) {
- case 0:
- clrbits_be16(&gpio->par_uart,
- ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
- setbits_be16(&gpio->par_uart,
- GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
- break;
- case 1:
- clrbits_be16(&gpio->par_uart,
- ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
- setbits_be16(&gpio->par_uart,
- GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi,
- ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
- break;
- }
-}
diff --git a/arch/m68k/cpu/mcf5227x/dspi.c b/arch/m68k/cpu/mcf5227x/dspi.c
deleted file mode 100644
index 8fc4da2..0000000
--- a/arch/m68k/cpu/mcf5227x/dspi.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2019
- * Angelo Dureghello <angleo@sysam.it>
- *
- * CPU specific dspi routines
- */
-
-#include <common.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_CF_DSPI
-void dspi_chip_select(int cs)
-{
- struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
- break;
- }
-}
-
-void dspi_chip_unselect(int cs)
-{
- struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- break;
- }
-}
-#endif /* CONFIG_CF_DSPI */
diff --git a/arch/m68k/cpu/mcf5227x/interrupts.c b/arch/m68k/cpu/mcf5227x/interrupts.c
deleted file mode 100644
index 5a6a88c..0000000
--- a/arch/m68k/cpu/mcf5227x/interrupts.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/* CPU specific interrupt routine */
-#include <common.h>
-#include <irq_func.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-
-int interrupt_init(void)
-{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
-
- /* Make sure all interrupts are disabled */
- setbits_be32(&intp->imrh0, 0xffffffff);
- setbits_be32(&intp->imrl0, 0xffffffff);
-
- enable_interrupts();
- return 0;
-}
-
-#if defined(CONFIG_MCFTMR)
-void dtimer_intr_setup(void)
-{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
-
- out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
- clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
-}
-#endif
diff --git a/arch/m68k/cpu/mcf5227x/speed.c b/arch/m68k/cpu/mcf5227x/speed.c
deleted file mode 100644
index fa9d5cb..0000000
--- a/arch/m68k/cpu/mcf5227x/speed.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-
-#include <asm/immap.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Low Power Divider specifications
- */
-#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
-#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
-
-#define CLOCK_PLL_FVCO_MAX 540000000
-#define CLOCK_PLL_FVCO_MIN 300000000
-
-#define CLOCK_PLL_FSYS_MAX 266666666
-#define CLOCK_PLL_FSYS_MIN 100000000
-#define MHZ 1000000
-
-void clock_enter_limp(int lpdiv)
-{
- ccm_t *ccm = (ccm_t *)MMAP_CCM;
- int i, j;
-
- /* Check bounds of divider */
- if (lpdiv < CLOCK_LPD_MIN)
- lpdiv = CLOCK_LPD_MIN;
- if (lpdiv > CLOCK_LPD_MAX)
- lpdiv = CLOCK_LPD_MAX;
-
- /* Round divider down to nearest power of two */
- for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
-
- /* Apply the divider to the system clock */
- clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
-
- /* Enable Limp Mode */
- setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
-}
-
-/*
- * brief Exit Limp mode
- * warning The PLL should be set and locked prior to exiting Limp mode
- */
-void clock_exit_limp(void)
-{
- ccm_t *ccm = (ccm_t *)MMAP_CCM;
- pll_t *pll = (pll_t *)MMAP_PLL;
-
- /* Exit Limp mode */
- clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
-
- /* Wait for the PLL to lock */
- while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
- ;
-}
-
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
-int get_clocks(void)
-{
-
- ccm_t *ccm = (ccm_t *)MMAP_CCM;
- pll_t *pll = (pll_t *)MMAP_PLL;
- int vco, temp, pcrvalue, pfdr;
- u8 bootmode;
-
- pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
- pfdr = pcrvalue >> 24;
-
- if (pfdr == 0x1E)
- bootmode = 0; /* Normal Mode */
-
-#ifdef CONFIG_CF_SBF
- bootmode = 3; /* Serial Mode */
-#endif
-
- if (bootmode == 0) {
- /* Normal mode */
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
- /* Default value */
- pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
- pcrvalue |= 0x1E << 24;
- out_be32(&pll->pcr, pcrvalue);
- vco =
- ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
- CONFIG_SYS_INPUT_CLKSRC;
- }
- gd->arch.vco_clk = vco; /* Vco clock */
- } else if (bootmode == 3) {
- /* serial mode */
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- gd->arch.vco_clk = vco; /* Vco clock */
- }
-
- if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
- /* Limp mode */
- } else {
- gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
-
- temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
- gd->cpu_clk = vco / temp; /* cpu clock */
-
- temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
- gd->arch.flb_clk = vco / temp; /* flexbus clock */
- gd->bus_clk = gd->arch.flb_clk;
- }
-
-#ifdef CONFIG_SYS_I2C_FSL
- gd->arch.i2c1_clk = gd->bus_clk;
-#endif
-
- return (0);
-}
diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
deleted file mode 100644
index 632f1b1..0000000
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ /dev/null
@@ -1,491 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#define _START _start
-#define _FAULT _fault
-
-#define SAVE_ALL \
- move.w #0x2700,%sr; /* disable intrs */ \
- subl #60,%sp; /* space for 15 regs */ \
- moveml %d0-%d7/%a0-%a6,%sp@;
-
-#define RESTORE_ALL \
- moveml %sp@,%d0-%d7/%a0-%a6; \
- addl #60,%sp; /* space for 15 regs */ \
- rte;
-
-#if defined(CONFIG_CF_SBF)
-#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
-#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
-#endif
-
-.text
-
-/*
- * Vector table. This is used for initial platform startup.
- * These vectors are to catch any un-intended traps.
- */
-_vectors:
-#if defined(CONFIG_CF_SBF)
-INITSP: .long 0 /* Initial SP */
-INITPC: .long ASM_DRAMINIT /* Initial PC */
-#else
-INITSP: .long 0 /* Initial SP */
-INITPC: .long _START /* Initial PC */
-#endif
-
-vector02_0F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-/* Reserved */
-vector10_17:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector18_1F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-#if !defined(CONFIG_CF_SBF)
-/* TRAP #0 - #15 */
-vector20_2F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-/* Reserved */
-vector30_3F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector64_127:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector128_191:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector192_255:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-#endif
-
-#if defined(CONFIG_CF_SBF)
- /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
-asm_sbf_img_hdr:
- .long 0x00000000 /* checksum, not yet implemented */
- .long 0x00020000 /* image length */
- .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
-
-asm_dram_init:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
- movec %d0, %RAMBAR1 /* init Rambar */
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
-
- /* Must disable global address */
- move.l #0xFC008000, %a1
- move.l #(CONFIG_SYS_CS0_BASE), (%a1)
- move.l #0xFC008008, %a1
- move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
- move.l #0xFC008004, %a1
- move.l #(CONFIG_SYS_CS0_MASK), (%a1)
-
- /*
- * Dram Initialization
- * a1, a2, and d0
- */
- move.l #0xFC0A4074, %a1
- move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
- nop
-
- /* SDRAM Chip 0 and 1 */
- move.l #0xFC0B8110, %a1
- move.l #0xFC0B8114, %a2
-
- /* calculate the size */
- move.l #0x13, %d1
- move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
-#ifdef CONFIG_SYS_SDRAM_BASE1
- lsr.l #1, %d2
-#endif
-
-dramsz_loop:
- lsr.l #1, %d2
- add.l #1, %d1
- cmp.l #1, %d2
- bne dramsz_loop
-
- /* SDRAM Chip 0 and 1 */
- move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
- or.l %d1, (%a1)
-#ifdef CONFIG_SYS_SDRAM_BASE1
- move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
- or.l %d1, (%a2)
-#endif
- nop
-
- /* dram cfg1 and cfg2 */
- move.l #0xFC0B8008, %a1
- move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
- nop
- move.l #0xFC0B800C, %a2
- move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
- nop
-
- move.l #0xFC0B8000, %a1 /* Mode */
- move.l #0xFC0B8004, %a2 /* Ctrl */
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Issue LEMR */
- move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
- nop
- move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
- nop
-
- move.l #1000, %d0
-wait1000:
- nop
- subq.l #1, %d0
- bne wait1000
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Perform two refresh cycles */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
- nop
- move.l %d0, (%a2)
- move.l %d0, (%a2)
- nop
-
- move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
- and.l #0x7FFFFFFF, %d0
- or.l #0x10000c00, %d0
- move.l %d0, (%a2)
- nop
-
- /*
- * DSPI Initialization
- * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
- * a1 - dspi status
- * a2 - dtfr
- * a3 - drfr
- * a4 - Dst addr
- */
-
- /* Enable pins for DSPI mode - chip-selects are enabled later */
- move.l #0xFC0A4036, %a0
- move.b #0x3F, %d0
- move.b %d0, (%a0)
-
- /* DSPI CS */
-#ifdef CONFIG_SYS_DSPI_CS0
- move.b (%a0), %d0
- or.l #0xC0, %d0
- move.b %d0, (%a0)
-#endif
-#ifdef CONFIG_SYS_DSPI_CS2
- move.l #0xFC0A4037, %a0
- move.b (%a0), %d0
- or.l #0x10, %d0
- move.b %d0, (%a0)
-#endif
- nop
-
- /* Configure DSPI module */
- move.l #0xFC05C000, %a0
- move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
-
- move.l #0xFC05C00C, %a0
- move.l #0x3E000011, (%a0)
-
- move.l #0xFC05C034, %a2 /* dtfr */
- move.l #0xFC05C03B, %a3 /* drfr */
-
- move.l #(ASM_SBF_IMG_HDR + 4), %a1
- move.l (%a1)+, %d5
- move.l (%a1), %a4
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
- move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
-
- move.l #0xFC05C02C, %a1 /* dspi status */
-
- /* Issue commands and address */
- move.l #0x8004000B, %d2 /* Fast Read Cmd */
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- move.l #0x80040000, %d2 /* Address byte 2 */
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- move.l #0x80040000, %d2 /* Address byte 1 */
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- move.l #0x80040000, %d2 /* Address byte 0 */
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- move.l #0x80040000, %d2 /* Dummy Wr and Rd */
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- /* Transfer serial boot header to sram */
-asm_dspi_rd_loop1:
- move.l #0x80040000, %d2
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- move.b %d1, (%a0) /* read, copy to dst */
-
- add.l #1, %a0 /* inc dst by 1 */
- sub.l #1, %d4 /* dec cnt by 1 */
- bne asm_dspi_rd_loop1
-
- /* Transfer u-boot from serial flash to memory */
-asm_dspi_rd_loop2:
- move.l #0x80040000, %d2
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- move.b %d1, (%a4) /* read, copy to dst */
-
- add.l #1, %a4 /* inc dst by 1 */
- sub.l #1, %d5 /* dec cnt by 1 */
- bne asm_dspi_rd_loop2
-
- move.l #0x00040000, %d2 /* Terminate */
- jsr asm_dspi_wr_status
- jsr asm_dspi_rd_status
-
- /* jump to memory and execute */
- move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
- move.l %a0, (%a1)
- jmp (%a0)
-
-asm_dspi_wr_status:
- move.l (%a1), %d0 /* status */
- and.l #0x0000F000, %d0
- cmp.l #0x00003000, %d0
- bgt asm_dspi_wr_status
-
- move.l %d2, (%a2)
- rts
-
-asm_dspi_rd_status:
- move.l (%a1), %d0 /* status */
- and.l #0x000000F0, %d0
- lsr.l #4, %d0
- cmp.l #0, %d0
- beq asm_dspi_rd_status
-
- move.b (%a3), %d1
- rts
-#endif /* CONFIG_CF_SBF */
-
-.text
- . = 0x400
-.globl _start
-_start:
- nop
- nop
- move.w #0x2700,%sr /* Mask off Interrupt */
-
- /* Set vector base register at the beginning of the Flash */
-#if defined(CONFIG_CF_SBF)
- move.l #CONFIG_SYS_TEXT_BASE, %d0
- movec %d0, %VBR
-#else
- move.l #CONFIG_SYS_FLASH_BASE, %d0
- movec %d0, %VBR
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
- movec %d0, %RAMBAR1
-#endif
-
- /* invalidate and disable cache */
- move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #0, %d0
- movec %d0, %ACR0
- movec %d0, %ACR1
-
- /* initialize general use internal ram */
- move.l #0, %d0
- move.l #(ICACHE_STATUS), %a1 /* icache */
- move.l #(DCACHE_STATUS), %a2 /* icache */
- move.l %d0, (%a1)
- move.l %d0, (%a2)
-
- /* put relocation table address to a5 */
- move.l #__got_start, %a5
-
- /* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
-
- /*
- * if configured, malloc_f arena will be reserved first,
- * then (and always) gd struct space will be reserved
- */
- move.l %sp, -(%sp)
- bsr board_init_f_alloc_reserve
-
- /* update stack and frame-pointers */
- move.l %d0, %sp
- move.l %sp, %fp
-
- /* initialize reserved area */
- move.l %d0, -(%sp)
- bsr board_init_f_init_reserve
-
- /* run low-level CPU init code (from flash) */
- bsr cpu_init_f
- clr.l %sp@-
-
- /* run low-level board init code (from flash) */
- move.l #board_init_f, %a1
- jsr (%a1)
-
- /* board_init_f() does not return */
-
-/******************************************************************************/
-
-/*
- * void relocate_code(addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
-.globl relocate_code
-relocate_code:
- link.w %a6,#0
- move.l 8(%a6), %sp /* set new stack pointer */
-
- move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
- move.l 16(%a6), %a0 /* Save copy of Destination Address */
-
- move.l #CONFIG_SYS_MONITOR_BASE, %a1
- move.l #__init_end, %a2
- move.l %a0, %a3
-
- /* copy the code to RAM */
-1:
- move.l (%a1)+, (%a3)+
- cmp.l %a1,%a2
- bgt.s 1b
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- move.l %a0, %a1
- add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
- jmp (%a1)
-
-in_ram:
-
-clear_bss:
- /*
- * Now clear BSS segment
- */
- move.l %a0, %a1
- add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a0, %d1
- add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
-6:
- clr.l (%a1)+
- cmp.l %a1,%d1
- bgt.s 6b
-
- /*
- * fix got table in RAM
- */
- move.l %a0, %a1
- add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a1,%a5 /* fix got pointer register a5 */
-
- move.l %a0, %a2
- add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
-
-7:
- move.l (%a1),%d1
- sub.l #_start,%d1
- add.l %a0,%d1
- move.l %d1,(%a1)+
- cmp.l %a2, %a1
- bne 7b
-
- /* calculate relative jump to board_init_r in ram */
- move.l %a0, %a1
- add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
-
- /* set parameters for board_init_r */
- move.l %a0,-(%sp) /* dest_addr */
- move.l %d0,-(%sp) /* gd */
- jsr (%a1)
-
-/******************************************************************************/
-
-/* exception code */
-.globl _fault
-_fault:
- bra _fault
-
-.globl _exc_handler
-_exc_handler:
- SAVE_ALL
- movel %sp,%sp@-
- bsr exc_handler
- addql #4,%sp
- RESTORE_ALL
-
-.globl _int_handler
-_int_handler:
- SAVE_ALL
- movel %sp,%sp@-
- bsr int_handler
- addql #4,%sp
- RESTORE_ALL
-
-/******************************************************************************/
-
-.align 4
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 645f7cb..25e9968 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -19,7 +19,7 @@
mts rslr, r8
#if defined(CONFIG_SPL_BUILD)
- addi r1, r0, CONFIG_SPL_STACK_ADDR
+ addi r1, r0, CONFIG_SPL_STACK
#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
#endif
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 6502aeb..32c436f 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -3,9 +3,7 @@
head-y := arch/mips/cpu/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq ($(CONFIG_SPL_START_S_PATH),)
-head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
-endif
+head-$(CONFIG_ARCH_JZ47XX) := arch/mips/mach-jz47xx/start.o
endif
libs-y += arch/mips/cpu/
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 47251a5..2acc21d 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -10,11 +10,7 @@
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
-
-#ifndef CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_SP_OFFSET)
-#endif
+#include <system-constants.h>
#ifdef CONFIG_32BIT
# define STATUS_SET 0
@@ -44,7 +40,7 @@
.macro setup_stack_gd
li t0, -16
- PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
+ PTR_LI t1, SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
PTR_SUBU \
sp, sp, GD_SIZE # reserve space for gd
diff --git a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
index 83cd8fa..cb369fb 100644
--- a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
+++ b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S
@@ -12,16 +12,11 @@
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/asm.h>
+#include <system-constants.h>
#include "mt7628.h"
-/* Set temporary stack address range */
-#ifndef CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_SP_OFFSET)
-#endif
-
#define CACHE_STACK_SIZE 0x4000
-#define CACHE_STACK_BASE (CONFIG_SYS_INIT_SP_ADDR - CACHE_STACK_SIZE)
+#define CACHE_STACK_BASE (SYS_INIT_SP_ADDR - CACHE_STACK_SIZE)
#define DELAY_USEC(us) ((58 * (us)) / 3)
@@ -134,7 +129,7 @@
#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
/* Set malloc base */
- li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
+ li t0, (SYS_INIT_SP_ADDR + 15) & (~15)
PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 7c4ef76..1255f53 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -8,10 +8,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
extra-y = start.o
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index e6dcb8a..e3e1bfd 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm-offsets.h>
#include <mpc83xx.h>
+#include <system-constants.h>
#include <ioports.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -138,7 +139,7 @@
0;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ gd = (gd_t *)SYS_INIT_SP_ADDR;
/* global data region was cleared in start.S */
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 11b1e61..d8f6cfe 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -7,6 +7,7 @@
#include <asm-offsets.h>
#include <clock_legacy.h>
#include <mpc83xx.h>
+#include <system-constants.h>
#include <time.h>
#include <asm/global_data.h>
@@ -25,7 +26,7 @@
void cpu_init_f (volatile immap_t * im)
{
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ gd = (gd_t *)SYS_INIT_SP_ADDR;
/* global data region was cleared in start.S */
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 0944d19..8a351b9 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -13,6 +13,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
+#include <system-constants.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@@ -39,7 +40,7 @@
#endif
#if defined(CONFIG_NAND_SPL) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+ (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
#define MINIMAL_SPL
#endif
@@ -229,8 +230,8 @@
/* set up the stack pointer in our newly created
* cache-ram; use r3 to keep the new SP for now to
* avoid overiding the SP it uselessly */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
+ lis r3, SYS_INIT_SP_ADDR@h
+ ori r3, r3, SYS_INIT_SP_ADDR@l
/* r4 = end of GD area */
addi r4, r3, GENERATED_GBL_DATA_SIZE
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index c32cde0..f3ee7d3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -9,10 +9,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
extra-y = start.o resetvec.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index a82516a..ba9736e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -344,6 +344,7 @@
}
+#ifndef CONFIG_WDT
#if defined(CONFIG_WATCHDOG)
#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
void
@@ -372,6 +373,7 @@
enable_interrupts();
}
#endif /* CONFIG_WATCHDOG */
+#endif
/*
* Initializes on-chip MMC controllers.
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 5a0d33b..1bba216 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <system-constants.h>
#include <asm-offsets.h>
#include <asm/global_data.h>
#include <asm/processor.h>
@@ -94,7 +95,7 @@
#endif
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ gd = (gd_t *)SYS_INIT_SP_ADDR;
/* gd area was zeroed during startup */
@@ -177,7 +178,7 @@
invalidate_tlb(1);
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
- !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
+ !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
!defined(CONFIG_NAND_SPL)
disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 2b2ad97..9a28269 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -14,6 +14,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
+#include <system-constants.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@@ -27,7 +28,7 @@
#define LAW_EN 0x80000000
#if defined(CONFIG_NAND_SPL) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+ (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
#define MINIMAL_SPL
#endif
@@ -1160,8 +1161,8 @@
bne 1b
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
- lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
- ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+ lis r4,SYS_INIT_SP_ADDR@h
+ ori r4,r4,SYS_INIT_SP_ADDR@l
addi r3,r3,16 /* Pre-relocation malloc area */
stw r3,GD_MALLOC_BASE(r4)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 550d45d..4f6778c 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -44,7 +44,7 @@
}
#if !defined(CONFIG_NAND_SPL) && \
- (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
+ (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index bec891d..e3a536d 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -5,10 +5,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
ifdef MINIMAL
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index cf03f41..713ff17 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -79,7 +79,7 @@
}
#if !defined(CONFIG_NAND_SPL) && \
- (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
+ (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
@@ -110,7 +110,7 @@
}
#if !defined(CONFIG_NAND_SPL) && \
- (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
+ (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 1c3f787..0d0cd22 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -56,6 +56,24 @@
/include/ "pq3-duart-0.dtsi"
/include/ "pq3-gpio-0.dtsi"
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p2020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2 0 0>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p2020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupts = <18 2 0 0>;
+ };
+
L2: l2-cache-controller@20000 {
compatible = "fsl,p2020-l2-cache-controller";
reg = <0x20000 0x1000>;
@@ -64,6 +82,9 @@
interrupts = <16 2 0 0>;
};
+/include/ "pq3-dma-0.dtsi"
+/include/ "pq3-dma-1.dtsi"
+
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-timer-0.dtsi"
@@ -73,6 +94,21 @@
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
+
+/include/ "pq3-sec3.1-0.dtsi"
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+
+ global-utilities@e0000 {
+ compatible = "fsl,p2020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ pmc: power@e0070 {
+ compatible = "fsl,mpc8548-pmc";
+ reg = <0xe0070 0x20>;
+ };
};
/* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/pq3-dma-0.dtsi b/arch/powerpc/dts/pq3-dma-0.dtsi
new file mode 100644
index 0000000..b5b37ad
--- /dev/null
+++ b/arch/powerpc/dts/pq3-dma-0.dtsi
@@ -0,0 +1,66 @@
+/*
+ * PQ3 DMA device tree stub [ controller @ offset 0x21000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <20 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <21 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <22 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <23 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-dma-1.dtsi b/arch/powerpc/dts/pq3-dma-1.dtsi
new file mode 100644
index 0000000..28cb8a5
--- /dev/null
+++ b/arch/powerpc/dts/pq3-dma-1.dtsi
@@ -0,0 +1,66 @@
+/*
+ * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <76 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <77 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <78 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <79 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-mpic-timer-B.dtsi b/arch/powerpc/dts/pq3-mpic-timer-B.dtsi
new file mode 100644
index 0000000..8734cff
--- /dev/null
+++ b/arch/powerpc/dts/pq3-mpic-timer-B.dtsi
@@ -0,0 +1,42 @@
+/*
+ * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+timer@42100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x42100 0x100 0x42300 4>;
+ interrupts = <4 0 3 0
+ 5 0 3 0
+ 6 0 3 0
+ 7 0 3 0>;
+};
diff --git a/arch/powerpc/dts/pq3-mpic.dtsi b/arch/powerpc/dts/pq3-mpic.dtsi
new file mode 100644
index 0000000..71c30eb
--- /dev/null
+++ b/arch/powerpc/dts/pq3-mpic.dtsi
@@ -0,0 +1,79 @@
+/*
+ * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+};
+
+timer@41100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x41100 0x100 0x41300 4>;
+ interrupts = <0 0 3 0
+ 1 0 3 0
+ 2 0 3 0
+ 3 0 3 0>;
+};
+
+message@41400 {
+ compatible = "fsl,mpic-v3.1-msgr";
+ reg = <0x41400 0x200>;
+ interrupts = <
+ 0xb0 2 0 0
+ 0xb1 2 0 0
+ 0xb2 2 0 0
+ 0xb3 2 0 0>;
+};
+
+msi@41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+};
diff --git a/arch/powerpc/dts/pq3-sec3.1-0.dtsi b/arch/powerpc/dts/pq3-sec3.1-0.dtsi
new file mode 100644
index 0000000..8f0a566
--- /dev/null
+++ b/arch/powerpc/dts/pq3-sec3.1-0.dtsi
@@ -0,0 +1,45 @@
+/*
+ * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0",
+ "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
+ "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 0 0 58 2 0 0>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+};
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 39fbc04..9e2f2d5 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -78,6 +78,7 @@
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
+ LAW_TRGT_IF_PCIE_1 = 0x02,
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 2e6255f..b0aafdc 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -447,7 +447,7 @@
(((ts) << 12) & MAS1_TS) |\
(MAS1_TSIZE(tsize)))
#define FSL_BOOKE_MAS2(epn, wimge) \
- (((epn) & MAS3_RPN) | (wimge))
+ (((epn) & MAS2_EPN) | (wimge))
#define FSL_BOOKE_MAS3(rpn, user, perms) \
(((rpn) & MAS3_RPN) | (user) | (perms))
#define FSL_BOOKE_MAS7(rpn) \
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 2782740..066d7f4 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -10,10 +10,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
obj-y += bdinfo.o
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 3b43066..d365705 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -137,7 +137,8 @@
if (size < bootm_size) {
ulong base = bootmap_base + size;
- printf("WARNING: adjusting available memory to %lx\n", size);
+ printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n",
+ size, (unsigned long long)bootm_size);
lmb_reserve(lmb, base, bootm_size - size);
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 76850ec..f2ef556 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -13,6 +13,7 @@
#include <config.h>
#include <common.h>
#include <elf.h>
+#include <system-constants.h>
#include <asm/encoding.h>
#include <generated/asm-offsets.h>
@@ -94,7 +95,7 @@
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
li t1, CONFIG_SPL_STACK
#else
- li t1, CONFIG_SYS_INIT_SP_ADDR
+ li t1, SYS_INIT_SP_ADDR
#endif
and sp, t1, t0 /* force 16 byte alignment */
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 18fde1c..21f00fc 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -63,7 +63,6 @@
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 00];
};
host-fs {
diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts
index ec53106..3eb0457 100644
--- a/arch/sandbox/dts/sandbox64.dts
+++ b/arch/sandbox/dts/sandbox64.dts
@@ -58,7 +58,6 @@
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x0 0x10002000 0x0 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 00];
};
i2c_0: i2c@0 {
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 8f93775..e068d0c 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -28,6 +28,9 @@
ethernet3 = ð_3;
ethernet4 = &dsa_eth0;
ethernet5 = ð_5;
+ ethernet6 = "/eth@10004000";
+ ethernet7 = &swp_1;
+ ethernet8 = &phy_eth0;
gpio1 = &gpio_a;
gpio2 = &gpio_b;
gpio3 = &gpio_c;
@@ -524,31 +527,31 @@
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 00];
};
eth_5: eth@10003000 {
compatible = "sandbox,eth";
reg = <0x10003000 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 11];
+ nvmem-cells = <ð5_addr>;
+ nvmem-cell-names = "mac-address";
};
eth_3: sbe5 {
compatible = "sandbox,eth";
reg = <0x10005000 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 33];
+ nvmem-cells = <ð3_addr>;
+ nvmem-cell-names = "mac-address";
};
eth@10004000 {
compatible = "sandbox,eth";
reg = <0x10004000 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 22];
};
phy_eth0: phy-test-eth {
compatible = "sandbox,eth";
reg = <0x10007000 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 77];
+ mac-address = [ 02 00 11 22 33 49 ];
phy-handle = <ðphy1>;
phy-mode = "2500base-x";
};
@@ -556,7 +559,8 @@
dsa_eth0: dsa-test-eth {
compatible = "sandbox,eth";
reg = <0x10006000 0x1000>;
- fake-host-hwaddr = [00 00 66 44 22 66];
+ nvmem-cells = <ð4_addr>;
+ nvmem-cell-names = "mac-address";
};
dsa-test {
@@ -700,6 +704,8 @@
pinctrl-0 = <&pinmux_i2c0_pins>;
eeprom@2c {
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x2c>;
compatible = "i2c-eeprom";
sandbox,emul = <&emul_eeprom>;
@@ -711,12 +717,22 @@
reg = <10 2>;
};
};
+
+ eth3_addr: mac-address@24 {
+ reg = <24 6>;
+ };
};
rtc_0: rtc@43 {
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x43>;
compatible = "sandbox-rtc";
sandbox,emul = <&emul0>;
+
+ eth4_addr: mac-address@40 {
+ reg = <0x40 6>;
+ };
};
rtc_1: rtc@61 {
@@ -898,7 +914,13 @@
};
misc-test {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "sandbox,misc_sandbox";
+
+ eth5_addr: mac-address@10 {
+ reg = <0x10 6>;
+ };
};
mmc2 {
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
index d25dc7c..bf5a585 100644
--- a/arch/sandbox/include/asm/spl.h
+++ b/arch/sandbox/include/asm/spl.h
@@ -6,8 +6,6 @@
#ifndef __asm_spl_h
#define __asm_spl_h
-#define CONFIG_SPL_BOARD_LOAD_IMAGE
-
enum {
BOOT_DEVICE_BOARD,
};
diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c
index 5d7d26b..9a55026 100644
--- a/arch/x86/cpu/apollolake/cpu_common.c
+++ b/arch/x86/cpu/apollolake/cpu_common.c
@@ -72,7 +72,7 @@
}
#ifdef CONFIG_DEBUG_UART
- apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
+ apl_uart_init(PCH_DEV_UART, CONFIG_VAL(DEBUG_UART_BASE));
#endif
}
diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h
index cc6cac0..483cf70 100644
--- a/arch/x86/include/asm/spl.h
+++ b/arch/x86/include/asm/spl.h
@@ -7,8 +7,6 @@
#ifndef __asm_spl_h
#define __asm_spl_h
-#define CONFIG_SPL_BOARD_LOAD_IMAGE
-
enum {
BOOT_DEVICE_SPI_MMAP = 10,
BOOT_DEVICE_FAST_SPI,
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 91eec35..36b67f0 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -27,6 +27,10 @@
config SPL_OPENSBI_LOAD_ADDR
default 0x01000000
+config SYS_FDT_BASE
+ hex
+ default 0x800f0000 if OF_SEPARATE
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index f129ebd..0a1b2c9 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -28,12 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
#ifdef CONFIG_NAND_MXS
static void setup_gpmi_nand(void)
{
@@ -69,12 +63,6 @@
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
init_uart_clk(2);
return 0;
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12266b2..a93cc93 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -59,31 +59,6 @@
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -124,12 +99,8 @@
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -139,6 +110,8 @@
hang();
}
+ preloader_console_init();
+
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index bb51be0..029f71b 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -68,34 +68,17 @@
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
/* Claiming pwm pins prevents LCD flicker during startup*/
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(1);
return 0;
@@ -114,14 +97,14 @@
timer_init();
- preloader_console_init();
-
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* DDR initialization */
diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig
new file mode 100644
index 0000000..63d4252
--- /dev/null
+++ b/board/broadcom/bcmbca/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+config SYS_BOARD
+ default "bcmbca"
+
+config SYS_VENDOR
+ default "broadcom"
+
+if TARGET_BCM947622
+
+config SYS_CONFIG_NAME
+ default "bcm947622"
+
+endif
diff --git a/board/broadcom/bcmbca/Makefile b/board/broadcom/bcmbca/Makefile
new file mode 100644
index 0000000..8f06c31
--- /dev/null
+++ b/board/broadcom/bcmbca/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+
+obj-y += board.o
diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c
new file mode 100644
index 0000000..4aa1d65
--- /dev/null
+++ b/board/broadcom/bcmbca/board.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ puts("fdtdec_setup_mem_size_base() has failed\n");
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c
index 2dc62d6..d2d2026 100644
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -83,31 +83,6 @@
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -149,14 +124,10 @@
arch_cpu_init();
- board_early_init_f();
-
init_uart_clk(2);
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -166,6 +137,8 @@
hang();
}
+ preloader_console_init();
+
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile
index d4ddfbf..2db0fc1 100644
--- a/board/congatec/common/Makefile
+++ b/board/congatec/common/Makefile
@@ -8,10 +8,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
ifdef MINIMAL
# necessary to create built-in.o
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index 8f04911..f6b9de2 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -11,7 +11,7 @@
LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+ LENGTH = 0x1080000 }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index d407f0b..7a4c08c 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -9,7 +9,6 @@
#include <net.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <bootm.h>
@@ -78,11 +77,6 @@
#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
-/*
- * Get a global data pointer
- */
-DECLARE_GLOBAL_DATA_PTR;
-
#define KS_CCR 0x08
#define KS_CCR_EEPROM BIT(9)
#define KS_BE0 BIT(12)
@@ -96,14 +90,15 @@
bool skip_eth0 = false;
bool skip_eth1 = false;
struct udevice *dev;
- int off, ret;
+ int ret;
+ ofnode node;
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
if (ret) /* ethaddr is already set */
skip_eth0 = true;
- off = fdt_path_offset(gd->fdt_blob, "ethernet1");
- if (off < 0) {
+ node = ofnode_path("ethernet1");
+ if (!ofnode_valid(node)) {
/* ethernet1 is not present in the system */
skip_eth1 = true;
goto out_set_ethaddr;
@@ -116,7 +111,7 @@
goto out_set_ethaddr;
}
- ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
+ ret = ofnode_device_is_compatible(node, "micrel,ks8851-mll");
if (ret)
goto out_set_ethaddr;
@@ -127,7 +122,7 @@
* MAC address.
*/
u32 reg, cider, ccr;
- reg = fdt_get_base_address(gd->fdt_blob, off);
+ reg = ofnode_get_addr(node);
if (!reg)
goto out_set_ethaddr;
@@ -149,13 +144,13 @@
if (skip_eth0 && skip_eth1)
return 0;
- off = fdt_path_offset(gd->fdt_blob, "eeprom0");
- if (off < 0) {
+ node = ofnode_path("eeprom0");
+ if (!ofnode_valid(node)) {
printf("%s: No eeprom0 path offset\n", __func__);
- return off;
+ return -ENOENT;
}
- ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
if (ret) {
printf("Cannot find EEPROM!\n");
return ret;
@@ -191,8 +186,8 @@
mode = "basic";
printf("Board: stm32mp1 in %s mode", mode);
- fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
- &fdt_compat_len);
+ fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+ &fdt_compat_len);
if (fdt_compat && fdt_compat_len)
printf(" (%s)", fdt_compat);
puts("\n");
@@ -289,7 +284,7 @@
const char *compat;
char test[128];
- compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
+ compat = ofnode_get_property(ofnode_root(), "compatible", NULL);
snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
compat, somcode, brdcode);
@@ -604,14 +599,13 @@
#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n) ((((n) - 1) & 3) * 2)
static int board_get_regulator_buck3_nvm_uv_av96(int *uv)
{
- const void *fdt = gd->fdt_blob;
struct udevice *dev;
u8 bucks_vout = 0;
const char *prop;
int len, ret;
/* Check whether this is Avenger96 board. */
- prop = fdt_getprop(fdt, 0, "compatible", &len);
+ prop = ofnode_get_property(ofnode_root(), "compatible", &len);
if (!prop || !len)
return -ENODEV;
@@ -701,8 +695,8 @@
const void *fdt_compat;
int fdt_compat_len;
- fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
- &fdt_compat_len);
+ fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+ &fdt_compat_len);
if (fdt_compat && fdt_compat_len) {
if (strncmp(fdt_compat, "st,", 3) != 0)
env_set("board_name", fdt_compat);
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 2b483da..1054837 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -273,7 +273,7 @@
setup_early_clocks();
/* done by pin controller driver if not debugging */
- enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
+ enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE));
}
#endif
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
index f9be769..1846134 100644
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@@ -54,19 +54,9 @@
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
+ return 0;
}
void board_init_f(ulong dummy)
@@ -81,8 +71,6 @@
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -92,6 +80,8 @@
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* DDR initialization */
diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c
index 20d8603..0a3e580 100644
--- a/board/engicam/stm32mp1/stm32mp1.c
+++ b/board/engicam/stm32mp1/stm32mp1.c
@@ -14,8 +14,6 @@
#include <asm/arch/sys_proto.h>
#include <power/regulator.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
char *mode;
@@ -28,8 +26,8 @@
mode = "basic";
printf("Board: stm32mp1 in %s mode", mode);
- fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
- &fdt_compat_len);
+ fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+ &fdt_compat_len);
if (fdt_compat && fdt_compat_len)
printf(" (%s)", fdt_compat);
puts("\n");
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 4df4849..4214c6e 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -6,10 +6,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
ifdef MINIMAL
# necessary to create built-in.o
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 71a086e..1a7806f 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019, 2021 NXP
+ * Copyright 2019-2022 NXP
*/
#include <common.h>
@@ -328,3 +328,8 @@
return 0;
}
#endif
+
+void *video_hw_init(void)
+{
+ return NULL;
+}
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 36b34c7..a00806e 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -5,10 +5,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
ifdef MINIMAL
obj-y += spl_minimal.o
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 7eaa204..8869500 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -57,24 +57,24 @@
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+ relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ gd = (gd_t *)CONFIG_VAL(GD_ADDR);
struct bd_info *bd;
memset(gd, 0, sizeof(gd_t));
- bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
arch_cpu_init();
get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
+ mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR),
+ CONFIG_VAL(RELOC_MALLOC_SIZE));
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 04faefe..7992666 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -72,8 +72,7 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index a7736d8..cbdb250 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -5,10 +5,12 @@
MINIMAL=
ifdef CONFIG_SPL_BUILD
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
+endif
ifdef MINIMAL
obj-y += spl_minimal.o
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 6665aa4..947bbc9 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -83,6 +83,12 @@
#define CPLD_FXS_LED 0x0F
#define CPLD_SYS_RST 0x00
+void board_reset(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ out_8(&cpld_data->system_rst, 1);
+}
+
void board_cpld_init(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -154,7 +160,9 @@
clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
+#endif
board_gpio_init();
board_cpld_init();
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 22156f2..b60027e 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -63,24 +63,24 @@
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+ relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ gd = (gd_t *)CONFIG_VAL(GD_ADDR);
struct bd_info *bd;
memset(gd, 0, sizeof(gd_t));
- bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;
arch_cpu_init();
get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
+ mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR),
+ CONFIG_VAL(RELOC_MALLOC_SIZE));
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_ENV_SUPPORT
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 5931ec6..6ded38a 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -77,8 +77,7 @@
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 6e6ce01..4c0feb4 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -87,33 +87,6 @@
ddr_init(dram_timing);
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-#ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#endif
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
/*
* Model specific PMIC adjustments necessary prior to DRAM init
*
@@ -253,8 +226,6 @@
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index 863c07d..f22faee 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -11,6 +11,9 @@
menu "KM Board Setup"
+config HUSH_INIT_VAR
+ def_bool y
+
config KM_PNVRAM
hex "Pseudo RAM"
default 0x80000
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index 4ef03c8..63361f1 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -32,8 +32,6 @@
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
@@ -51,15 +49,6 @@
IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
};
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -222,19 +211,6 @@
printf("Failed to find clock node. Check device tree\n");
}
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -269,12 +245,8 @@
init_uart_clk(2);
- board_early_init_f();
-
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -284,6 +256,8 @@
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* PMIC initialization */
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c
index 4142699..315d9f9 100644
--- a/board/kontron/sl28/ddr.c
+++ b/board/kontron/sl28/ddr.c
@@ -54,6 +54,9 @@
.ddr_cdr1 = 0x80040000,
.ddr_cdr2 = 0x0000bc01,
+
+ /* Erratum A-009942, set optimal CPO value */
+ .debug[28] = 0x00700040,
};
int fsl_initdram(void)
@@ -66,11 +69,17 @@
dram_size = 0x80000000;
ddr_cfg_regs.cs[1].bnds = 0;
ddr_cfg_regs.cs[1].config = 0;
- ddr_cfg_regs.cs[1].config_2 = 0;
break;
case GPPORCR1_MEM_4GB_CS0_1:
dram_size = 0x100000000ULL;
break;
+ case GPPORCR1_MEM_8GB_CS0_1:
+ dram_size = 0x200000000ULL;
+ ddr_cfg_regs.cs[0].bnds = 0x000000ff;
+ ddr_cfg_regs.cs[0].config = 0x80044403;
+ ddr_cfg_regs.cs[1].bnds = 0x010001ff;
+ ddr_cfg_regs.cs[1].config = 0x80044403;
+ break;
case GPPORCR1_MEM_512MB_CS0:
dram_size = 0x20000000;
fallthrough; /* for now */
@@ -80,7 +89,6 @@
case GPPORCR1_MEM_4GB_CS0_2:
dram_size = 0x100000000ULL;
fallthrough; /* for now */
- case GPPORCR1_MEM_8GB_CS0_1:
case GPPORCR1_MEM_8GB_CS0_1_2_3:
dram_size = 0x200000000ULL;
fallthrough; /* for now */
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index d54145e..d87ab6d 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -57,31 +57,6 @@
return 0;
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -90,10 +65,6 @@
init_uart_clk(2);
- board_early_init_f();
-
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -103,6 +74,8 @@
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* DDR initialization */
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index 19c486e..faed6fc 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -89,31 +89,6 @@
return 0;
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
- MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -122,8 +97,6 @@
init_uart_clk(0);
- board_early_init_f();
-
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
diff --git a/board/sandbox/sandbox.env b/board/sandbox/sandbox.env
index b4c0463..a2c1970 100644
--- a/board/sandbox/sandbox.env
+++ b/board/sandbox/sandbox.env
@@ -6,10 +6,6 @@
stderr=serial,vidconsole
ethaddr=02:00:11:22:33:44
-eth2addr=02:00:11:22:33:48
-eth3addr=02:00:11:22:33:45
-eth4addr=02:00:11:22:33:48
-eth5addr=02:00:11:22:33:46
eth6addr=02:00:11:22:33:47
ipaddr=192.0.2.1
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index 5fb1be2..d52dce4 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -202,18 +202,4 @@
STPMIC1_BUCKS_MRST_CR,
STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
-
- /* Check if debug is enabled to program PMIC according to the bit */
- if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
- log_info("Keep debug unit ON\n");
-
- pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
- STPMIC1_MRST_BUCK_DEBUG,
- STPMIC1_MRST_BUCK_DEBUG);
-
- if (STPMIC1_MRST_LDO_DEBUG)
- pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
- STPMIC1_MRST_LDO_DEBUG,
- STPMIC1_MRST_LDO_DEBUG);
- }
}
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
index 89e97ae..6ab8f80 100644
--- a/board/st/stm32mp1/Kconfig
+++ b/board/st/stm32mp1/Kconfig
@@ -11,3 +11,18 @@
source "board/st/common/Kconfig"
endif
+
+if TARGET_ST_STM32MP13x
+
+config SYS_BOARD
+ default "stm32mp1"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp13_st_common"
+
+source "board/st/common/Kconfig"
+
+endif
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
index 6451195..d5a09cd 100644
--- a/board/st/stm32mp1/MAINTAINERS
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -3,10 +3,14 @@
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
+F: arch/arm/dts/stm32mp13*
F: arch/arm/dts/stm32mp15*
F: board/st/stm32mp1/
+F: configs/stm32mp13_defconfig
F: configs/stm32mp15_defconfig
F: configs/stm32mp15_basic_defconfig
F: configs/stm32mp15_trusted_defconfig
+F: include/configs/stm32mp13_common.h
+F: include/configs/stm32mp13_st_common.h
F: include/configs/stm32mp15_common.h
F: include/configs/stm32mp15_st_common.h
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 07b1a63..9496890 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -82,11 +82,6 @@
#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
-/*
- * Get a global data pointer
- */
-DECLARE_GLOBAL_DATA_PTR;
-
#define USB_LOW_THRESHOLD_UV 200000
#define USB_WARNING_LOW_THRESHOLD_UV 660000
#define USB_START_LOW_THRESHOLD_UV 1230000
@@ -116,8 +111,8 @@
mode = "basic";
}
- fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
- &fdt_compat_len);
+ fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+ &fdt_compat_len);
log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
fdt_compat && fdt_compat_len ? fdt_compat : "");
@@ -554,8 +549,7 @@
clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
}
-/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
-static int dk2_i2c1_fix(void)
+static int board_stm32mp15x_dk2_init(void)
{
ofnode node;
struct gpio_desc hdmi, audio;
@@ -564,6 +558,7 @@
if (!IS_ENABLED(CONFIG_DM_REGULATOR))
return -ENODEV;
+ /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
if (!ofnode_valid(node)) {
log_debug("no hdmi-transmitter@39 ?\n");
@@ -611,7 +606,7 @@
return ret;
}
-static bool board_is_dk2(void)
+static bool board_is_stm32mp15x_dk2(void)
{
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
of_machine_is_compatible("st,stm32mp157c-dk2"))
@@ -620,7 +615,7 @@
return false;
}
-static bool board_is_ev1(void)
+static bool board_is_stm32mp15x_ev1(void)
{
if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
(of_machine_is_compatible("st,stm32mp157a-ev1") ||
@@ -644,7 +639,7 @@
.of_match = goodix_ids,
};
-static void board_ev1_init(void)
+static void board_stm32mp15x_ev1_init(void)
{
struct udevice *dev;
@@ -657,11 +652,11 @@
{
board_key_check();
- if (board_is_ev1())
- board_ev1_init();
+ if (board_is_stm32mp15x_ev1())
+ board_stm32mp15x_ev1_init();
- if (board_is_dk2())
- dk2_i2c1_fix();
+ if (board_is_stm32mp15x_dk2())
+ board_stm32mp15x_dk2_init();
if (IS_ENABLED(CONFIG_DM_REGULATOR))
regulators_enable_boot_on(_DEBUG);
@@ -690,8 +685,8 @@
int buf_len;
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
- fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
- &fdt_compat_len);
+ fdt_compat = ofnode_get_property(ofnode_root(), "compatible",
+ &fdt_compat_len);
if (fdt_compat && fdt_compat_len) {
if (strncmp(fdt_compat, "st,", 3) != 0) {
env_set("board_name", fdt_compat);
diff --git a/board/synopsys/iot_devkit/u-boot.lds b/board/synopsys/iot_devkit/u-boot.lds
index d083168..5aff100 100644
--- a/board/synopsys/iot_devkit/u-boot.lds
+++ b/board/synopsys/iot_devkit/u-boot.lds
@@ -5,6 +5,7 @@
*/
#include <config.h>
+#include <system-constants.h>
MEMORY {
ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig
new file mode 100644
index 0000000..87fed44
--- /dev/null
+++ b/board/ti/am62x/Kconfig
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+# Suman Anna <s-anna@ti.com>
+
+choice
+ prompt "TI K3 AM62x based boards"
+ optional
+
+config TARGET_AM625_A53_EVM
+ bool "TI K3 based AM625 EVM running on A53"
+ select ARM64
+ select SOC_K3_AM625
+
+config TARGET_AM625_R5_EVM
+ bool "TI K3 based AM625 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select SOC_K3_AM625
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_AM625_A53_EVM
+
+config SYS_BOARD
+ default "am62x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am62x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM625_R5_EVM
+
+config SYS_BOARD
+ default "am62x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am62x_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
new file mode 100644
index 0000000..105e741
--- /dev/null
+++ b/board/ti/am62x/MAINTAINERS
@@ -0,0 +1,8 @@
+AM62x BOARD
+M: Dave Gerlach <d-gerlach@ti.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+F: board/ti/am62x/
+F: include/configs/am62x_evm.h
+F: configs/am62x_evm_r5_defconfig
+F: configs/am62x_evm_a53_defconfig
diff --git a/board/ti/am62x/Makefile b/board/ti/am62x/Makefile
new file mode 100644
index 0000000..f4c35ed
--- /dev/null
+++ b/board/ti/am62x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+# Suman Anna <s-anna@ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
new file mode 100644
index 0000000..4dd5e64
--- /dev/null
+++ b/board/ti/am62x/evm.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM62x platforms
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Suman Anna <s-anna@ti.com>
+ *
+ */
+
+#include <asm/io.h>
+#include <spl.h>
+#include <fdt_support.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = 0x80000000;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x80000000;
+ gd->ram_size = 0x80000000;
+
+ return 0;
+}
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 96434b3..39b5c706 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -159,6 +159,7 @@
int misc_init_r(void)
{
twl4030_power_init();
+ twl4030_power_mmc_init(0);
#if defined(CONFIG_SMC911X)
setup_net_chip();
@@ -247,10 +248,3 @@
gpio_set_value(rst_gpio, 1);
}
#endif /* CONFIG_SMC911X */
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif /* CONFIG_MMC */
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index e6ff54c..105461e 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -109,11 +109,12 @@
static void __maybe_unused detect_enable_hyperflash(void *blob)
{
struct gpio_desc desc = {0};
+ char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
- if (dm_gpio_lookup_name("6", &desc))
+ if (dm_gpio_lookup_name(hypermux_sel_gpio, &desc))
return;
- if (dm_gpio_request(&desc, "6"))
+ if (dm_gpio_request(&desc, hypermux_sel_gpio))
return;
if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN))
@@ -132,7 +133,8 @@
}
#endif
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
+ defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM))
void spl_perform_fixups(struct spl_image_info *spl_image)
{
detect_enable_hyperflash(spl_image->fdt_addr);
@@ -490,6 +492,41 @@
}
#endif
+static int __maybe_unused detect_SW3_1_state(void)
+{
+ if (IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) {
+ struct gpio_desc desc = {0};
+ int ret;
+ char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
+
+ ret = dm_gpio_lookup_name(hypermux_sel_gpio, &desc);
+ if (ret) {
+ printf("error getting GPIO lookup name: %d\n", ret);
+ return ret;
+ }
+
+ ret = dm_gpio_request(&desc, hypermux_sel_gpio);
+ if (ret) {
+ printf("error requesting GPIO: %d\n", ret);
+ goto err_free_gpio;
+ }
+
+ ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+ if (ret) {
+ printf("error setting direction flag of GPIO: %d\n", ret);
+ goto err_free_gpio;
+ }
+
+ ret = dm_gpio_get_value(&desc);
+ if (ret < 0)
+ printf("error getting value of GPIO: %d\n", ret);
+
+err_free_gpio:
+ dm_gpio_free(desc.dev, &desc);
+ return ret;
+ }
+}
+
void spl_board_init(void)
{
#if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
@@ -522,4 +559,18 @@
printf("ESM PMIC init failed: %d\n", ret);
}
#endif
+ if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) &&
+ IS_ENABLED(CONFIG_HBMC_AM654)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = detect_SW3_1_state();
+ if (ret == 1) {
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(hbmc_am654),
+ &dev);
+ if (ret)
+ debug("Failed to probe hyperflash\n");
+ }
+ }
}
diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c
index 32703c5..41e7050 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -40,26 +40,8 @@
puts("Failed to find clock node. Check device tree\n");
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t uart_pads[] = {
- IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(3);
return 0;
@@ -78,14 +60,14 @@
timer_init();
- preloader_console_init();
-
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
+ preloader_console_init();
+
/* DDR initialization */
spl_dram_init();
diff --git a/boot/bootm.c b/boot/bootm.c
index 714406a..dfa65f1 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -498,7 +498,8 @@
}
#define CONSOLE_ARG "console="
-#define CONSOLE_ARG_SIZE sizeof(CONSOLE_ARG)
+#define NULL_CONSOLE (CONSOLE_ARG "ttynull")
+#define CONSOLE_ARG_SIZE sizeof(NULL_CONSOLE)
/**
* fixup_silent_linux() - Handle silencing the linux boot if required
@@ -550,21 +551,22 @@
char *end = strchr(start, ' ');
int start_bytes;
- start_bytes = start - cmdline + CONSOLE_ARG_SIZE - 1;
+ start_bytes = start - cmdline;
strncpy(buf, cmdline, start_bytes);
+ strncpy(buf + start_bytes, NULL_CONSOLE, CONSOLE_ARG_SIZE);
if (end)
- strcpy(buf + start_bytes, end);
+ strcpy(buf + start_bytes + CONSOLE_ARG_SIZE - 1, end);
else
- buf[start_bytes] = '\0';
+ buf[start_bytes + CONSOLE_ARG_SIZE] = '\0';
} else {
- sprintf(buf, "%s %s", cmdline, CONSOLE_ARG);
+ sprintf(buf, "%s %s", cmdline, NULL_CONSOLE);
}
if (buf + strlen(buf) >= cmdline)
return -ENOSPC;
} else {
- if (maxlen < sizeof(CONSOLE_ARG))
+ if (maxlen < CONSOLE_ARG_SIZE)
return -ENOSPC;
- strcpy(buf, CONSOLE_ARG);
+ strcpy(buf, NULL_CONSOLE);
}
debug("after silent fix-up: %s\n", buf);
diff --git a/boot/image-board.c b/boot/image-board.c
index 0d2e0fc..cfc1c65 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -21,10 +21,6 @@
#include <asm/cache.h>
#include <asm/global_data.h>
-#ifndef CONFIG_SYS_BARGSIZE
-#define CONFIG_SYS_BARGSIZE 512
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
@@ -827,6 +823,7 @@
return 0;
}
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
/**
* boot_get_cmdline - allocate and initialize kernel cmdline
* @lmb: pointer to lmb handle, will be used for memory mgmt
@@ -900,6 +897,7 @@
return 0;
}
+#endif
int image_setup_linux(bootm_headers_t *images)
{
diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c
index 78d8906..5ab9ae1 100644
--- a/boot/image-pre-load.c
+++ b/boot/image-pre-load.c
@@ -23,11 +23,6 @@
#define IMAGE_PRE_LOAD_PROP_PUBLIC_KEY "public-key"
#define IMAGE_PRE_LOAD_PROP_MANDATORY "mandatory"
-#ifndef CONFIG_SYS_BOOTM_LEN
-/* use 8MByte as default max gunzip size */
-#define CONFIG_SYS_BOOTM_LEN 0x800000
-#endif
-
/*
* Information in the device-tree about the signature in the header
*/
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 09193b6..9a0b720 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -71,6 +71,23 @@
printed when the command interpreter needs more input
to complete a command. Usually "> ".
+config SYS_MAXARGS
+ int "Maximum number arguments accepted by commands"
+ default 16
+
+config SYS_CBSIZE
+ int "Console input buffer size"
+ default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \
+ RCAR_GEN3 || TARGET_SOCFPGA_SOC64
+ default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \
+ FSL_LSCH3 || X86
+ default 256 if M68K || PPC
+ default 1024
+
+config SYS_PBSIZE
+ int "Buffer size for console output"
+ default 1044
+
config SYS_XTRACE
bool "Command execution tracer"
depends on CMDLINE
@@ -2552,6 +2569,7 @@
depends on CMD_UBI
default y if CMD_UBI
select LZO
+ select GZIP
help
UBIFS is a file system for flash devices which works on top of UBI.
diff --git a/cmd/dm.c b/cmd/dm.c
index 1dd19fe..ca60922 100644
--- a/cmd/dm.c
+++ b/cmd/dm.c
@@ -8,12 +8,6 @@
#include <common.h>
#include <command.h>
-#include <dm.h>
-#include <malloc.h>
-#include <mapmem.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <dm/root.h>
#include <dm/util.h>
static int do_dm_dump_all(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -64,55 +58,21 @@
return 0;
}
-static struct cmd_tbl test_commands[] = {
- U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""),
- U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""),
- U_BOOT_CMD_MKENT(devres, 1, 1, do_dm_dump_devres, "", ""),
- U_BOOT_CMD_MKENT(drivers, 1, 1, do_dm_dump_drivers, "", ""),
- U_BOOT_CMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat, "", ""),
- U_BOOT_CMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info, "", ""),
-};
-
-static __maybe_unused void dm_reloc(void)
-{
- static int relocated;
-
- if (!relocated) {
- fixup_cmdtable(test_commands, ARRAY_SIZE(test_commands));
- relocated = 1;
- }
-}
-
-static int do_dm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- struct cmd_tbl *test_cmd;
- int ret;
-
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- dm_reloc();
-#endif
-
- if (argc < 2)
- return CMD_RET_USAGE;
- test_cmd = find_cmd_tbl(argv[1], test_commands,
- ARRAY_SIZE(test_commands));
- argc -= 2;
- argv += 2;
- if (!test_cmd || argc > test_cmd->maxargs)
- return CMD_RET_USAGE;
-
- ret = test_cmd->cmd(test_cmd, flag, argc, argv);
-
- return cmd_process_error(test_cmd, ret);
-}
-
-U_BOOT_CMD(
- dm, 3, 1, do_dm,
- "Driver model low level access",
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+static char dm_help_text[] =
"tree Dump driver model tree ('*' = activated)\n"
"dm uclass Dump list of instances for each uclass\n"
"dm devres Dump list of device resources for each device\n"
"dm drivers Dump list of drivers with uclass and instances\n"
"dm compat Dump list of drivers with compatibility strings\n"
"dm static Dump list of drivers with static platform data"
-);
+ ;
+#endif
+
+U_BOOT_CMD_WITH_SUBCMDS(dm, "Driver model low level access", dm_help_text,
+ U_BOOT_SUBCMD_MKENT(tree, 1, 1, do_dm_dump_all),
+ U_BOOT_SUBCMD_MKENT(uclass, 1, 1, do_dm_dump_uclass),
+ U_BOOT_SUBCMD_MKENT(devres, 1, 1, do_dm_dump_devres),
+ U_BOOT_SUBCMD_MKENT(drivers, 1, 1, do_dm_dump_drivers),
+ U_BOOT_SUBCMD_MKENT(compat, 1, 1, do_dm_dump_driver_compat),
+ U_BOOT_SUBCMD_MKENT(static, 1, 1, do_dm_dump_static_driver_info));
diff --git a/cmd/qfw.c b/cmd/qfw.c
index d586150..ccbc967 100644
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@@ -25,15 +25,17 @@
qfw_read_entry(qfw_dev, FW_CFG_SETUP_SIZE, 4, &setup_size);
qfw_read_entry(qfw_dev, FW_CFG_KERNEL_SIZE, 4, &kernel_size);
- if (setup_size == 0 || kernel_size == 0) {
+ if (kernel_size == 0) {
printf("warning: no kernel available\n");
return -1;
}
data_addr = load_addr;
- qfw_read_entry(qfw_dev, FW_CFG_SETUP_DATA,
- le32_to_cpu(setup_size), data_addr);
- data_addr += le32_to_cpu(setup_size);
+ if (setup_size != 0) {
+ qfw_read_entry(qfw_dev, FW_CFG_SETUP_DATA,
+ le32_to_cpu(setup_size), data_addr);
+ data_addr += le32_to_cpu(setup_size);
+ }
qfw_read_entry(qfw_dev, FW_CFG_KERNEL_DATA,
le32_to_cpu(kernel_size), data_addr);
diff --git a/common/Kconfig b/common/Kconfig
index a96842a..84db2e4 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -659,6 +659,18 @@
help
Enabling this option calls 'misc_init_r' function
+config SYS_MALLOC_BOOTPARAMS
+ bool "Malloc a buffer to use for bootparams"
+ help
+ In some cases rather than using a known location to store the
+ bi_boot_params portion of gd we need to allocate it from our malloc pool.
+
+config SYS_BOOTPARAMS_LEN
+ hex "Size of the bootparam buffer to malloc in bytes"
+ depends on SYS_MALLOC_BOOTPARAMS
+ default 0x20000 if MIPS || RCAR_GEN3
+ default 0x10000
+
config ID_EEPROM
bool "Enable I2C connected system identifier EEPROM"
help
diff --git a/common/board_r.c b/common/board_r.c
index 6f4aca2..ed29069 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -457,7 +457,7 @@
return 0;
}
-#ifdef CONFIG_SYS_BOOTPARAMS_LEN
+#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS
static int initr_malloc_bootparams(void)
{
gd->bd->bi_boot_params = (ulong)malloc(CONFIG_SYS_BOOTPARAMS_LEN);
@@ -469,18 +469,6 @@
}
#endif
-#ifdef CONFIG_CMD_NET
-static int initr_ethaddr(void)
-{
- struct bd_info *bd = gd->bd;
-
- /* kept around for legacy kernels only ... ignore the next section */
- eth_env_get_enetaddr("ethaddr", bd->bi_enetaddr);
-
- return 0;
-}
-#endif /* CONFIG_CMD_NET */
-
#if defined(CONFIG_LED_STATUS)
static int initr_status_led(void)
{
@@ -612,6 +600,9 @@
*/
#endif
initr_reloc_global_data,
+#if CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC) && CONFIG_IS_ENABLED(EVENT)
+ event_manual_reloc,
+#endif
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
initr_unlock_ram_in_cache,
#endif
@@ -713,7 +704,7 @@
initr_pvblock,
#endif
initr_env,
-#ifdef CONFIG_SYS_BOOTPARAMS_LEN
+#ifdef CONFIG_SYS_MALLOC_BOOTPARAMS
initr_malloc_bootparams,
#endif
INIT_FUNC_WATCHDOG_RESET
@@ -756,9 +747,6 @@
initr_status_led,
#endif
/* PPC has a udelay(20) here dating from 2002. Why? */
-#ifdef CONFIG_CMD_NET
- initr_ethaddr,
-#endif
#if defined(CONFIG_GPIO_HOG)
gpio_hog_probe_all,
#endif
diff --git a/common/event.c b/common/event.c
index 9d67a06..af1ed41 100644
--- a/common/event.c
+++ b/common/event.c
@@ -17,6 +17,7 @@
#include <malloc.h>
#include <asm/global_data.h>
#include <linux/list.h>
+#include <relocate.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -148,6 +149,20 @@
}
}
+#if CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC)
+int event_manual_reloc(void)
+{
+ struct evspy_info *spy, *end;
+
+ spy = ll_entry_start(struct evspy_info, evspy_info);
+ end = ll_entry_end(struct evspy_info, evspy_info);
+ for (; spy < end; spy++)
+ MANUAL_RELOC(spy->func);
+
+ return 0;
+}
+#endif
+
#if CONFIG_IS_ENABLED(EVENT_DYNAMIC)
static void spy_free(struct event_spy *spy)
{
@@ -159,8 +174,6 @@
struct event_state *state = gd_event_state();
struct event_spy *spy;
- if (!CONFIG_IS_ENABLED(EVENT_DYNAMIC))
- return -ENOSYS;
spy = malloc(sizeof(*spy));
if (!spy)
return log_msg_ret("alloc", -ENOMEM);
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 50ff113..2ad2351 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1,5 +1,3 @@
-menu "SPL / TPL / VPL"
-
config SUPPORT_SPL
bool
@@ -13,15 +11,16 @@
bool
config SPL
- bool
+ bool "Enable SPL"
depends on SUPPORT_SPL
- prompt "Enable SPL"
help
If you want to build SPL as well as the normal image, say Y.
+menu "SPL configuration options"
+ depends on SPL
+
config SPL_FRAMEWORK
bool "Support SPL based upon the common SPL framework"
- depends on SPL
default y
help
Enable the SPL framework under common/spl/. This framework
@@ -39,7 +38,6 @@
config SPL_SIZE_LIMIT
hex "Maximum size of SPL image"
- depends on SPL
default 0x11000 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x0
@@ -75,6 +73,89 @@
of SRAM available for SPL when the stack required before reolcation
uses this SRAM, too.
+config SPL_MAX_SIZE
+ hex "Maximum size of the SPL image, excluding BSS"
+ default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
+ default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
+ default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
+ default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
+ default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
+ default 0x7000 if RCAR_GEN3
+ default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+ default 0x0
+ help
+ Maximum size of the SPL image (text, data, rodata, and linker lists
+ sections), BSS excluded. When defined, the linker checks that the
+ actual size does not exceed it.
+
+config SPL_PAD_TO
+ hex "Offset to which the SPL should be padded before appending the SPL payload"
+ default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
+ default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB)
+ default 0x10000 if ARCH_KEYSTONE
+ default 0x8000 if ARCH_SUNXI && !MACH_SUN50I_H616
+ default TPL_MAX_SIZE if TPL_MAX_SIZE > SPL_MAX_SIZE
+ default SPL_MAX_SIZE
+ help
+ Image offset to which the SPL should be padded before appending the
+ SPL payload. By default, this is defined as CONFIG_SPL_MAX_SIZE, or 0 if
+ CONFIG_SPL_MAX_SIZE is undefined. CONFIG_SPL_PAD_TO must be either
+ 0, meaning to append the SPL payload without any padding, or >=
+ CONFIG_SPL_MAX_SIZE.
+
+config SPL_HAS_BSS_LINKER_SECTION
+ depends on SPL_FRAMEWORK
+ bool "Use a specific address for the BSS via the linker script"
+ default y if ARCH_SUNXI || ARCH_MX6 || ARCH_OMAP2PLUS || MIPS || RISCV
+
+config SPL_BSS_START_ADDR
+ hex "Link address for the BSS within the SPL binary"
+ depends on SPL_HAS_BSS_LINKER_SECTION
+ default 0x88200000 if (ARCH_MX6 && (MX6SX || MX6SL || MX6UL || MX6ULL)) || ARCH_MX7
+ default 0x18200000 if ARCH_MX6 && !(MX6SX || MX6SL || MX6UL || MX6ULL)
+ default 0x80a00000 if ARCH_OMAP2PLUS
+ default 0x81f80000 if ARCH_SUNXI && MACH_SUNIV
+ default 0x4ff80000 if ARCH_SUNXI && !(MACH_SUN9I || MACH_SUNIV)
+ default 0x2ff80000 if ARCH_SUNXI && MACH_SUN9I
+
+choice
+ prompt "Enforce SPL BSS limit"
+ depends on !PPC
+ default SPL_BSS_LIMIT
+ help
+ In some platforms we only want to enforce a limit on the size of the
+ BSS in memory. On other platforms we need to enforce a limit on the
+ whole of the memory allocation as we're strictly limited to a small
+ typically non-DRAM location. Finally, other platforms do not enforce
+ a memory limit within SPL.
+
+config SPL_NO_BSS_LIMIT
+ bool "Do not enforce a build time limit on the size of the BSS"
+
+config SPL_BSS_LIMIT
+ bool "Enforce a limit on the size of the BSS only"
+
+config SPL_FOOTPRINT_LIMIT
+ bool "Enforce a limit on the whole of memory allocated to SPL, BSS included"
+
+endchoice
+
+config SPL_BSS_MAX_SIZE
+ hex "Maximum size in memory allocated to the SPL BSS"
+ depends on SPL_BSS_LIMIT
+ default 0x100000 if ARCH_MX6 || RISCV
+ default 0x80000 if ARCH_OMAP2PLUS || ARCH_SUNXI
+ help
+ When non-zero, the linker checks that the actual memory used by SPL
+ from __bss_start to __bss_end does not exceed it.
+
+config SPL_MAX_FOOTPRINT
+ hex "Maximum size in memory allocated to the SPL, BSS included"
+ depends on SPL_FOOTPRINT_LIMIT
+ help
+ When non-zero, the linker checks that the actual memory used by SPL
+ from _start to __bss_end does not exceed it.
+
config SPL_SYS_STACK_F_CHECK_BYTE
hex
default 0xaa
@@ -116,33 +197,11 @@
For this to work, you must have a U-Boot image in the binman image, so
binman can update SPL with the location of it.
-menu "PowerPC and LayerScape SPL Boot options"
-
-config SPL_NAND_BOOT
- bool "Load SPL from NAND flash"
- depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
-
-config SPL_MMC_BOOT
- bool "Load SPL from SD Card / eMMC"
- depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
-
-config SPL_SPI_BOOT
- bool "Load SPL from SPI flash"
- depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
-
-config SPL_FSL_PBL
- bool "Create SPL in Freescale PBI format"
- depends on (PPC || ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && \
- SUPPORT_SPL
- help
- Create boot binary having SPL binary in PBI format concatenated with
- u-boot binary.
-
-endmenu
+source "common/spl/Kconfig.nxp"
config HANDOFF
bool "Pass hand-off information from SPL to U-Boot proper"
- depends on SPL && BLOBLIST
+ depends on BLOBLIST
help
It is useful to be able to pass information from SPL to U-Boot
proper to preserve state that is known in SPL and is needed in U-Boot.
@@ -150,8 +209,6 @@
in boot. It is available in gd->handoff. The state state is set up
in SPL (or TPL if that is being used).
-if SPL
-
config SPL_HANDOFF
bool "Pass hand-off information from SPL to U-Boot proper"
depends on HANDOFF && SPL_BLOBLIST
@@ -189,13 +246,6 @@
spl_board_init() from board_init_r(). This function should be
provided by the board.
-config VPL_BOARD_INIT
- bool "Call board-specific initialization in VPL"
- help
- If this option is enabled, U-Boot will call the function
- spl_board_init() from board_init_r(). This function should be
- provided by the board.
-
config SPL_BOOTROM_SUPPORT
bool "Support returning to the BOOTROM"
help
@@ -246,23 +296,33 @@
are correct, without further integrity checks.
config SPL_SYS_MALLOC_SIMPLE
- bool
- prompt "Only use malloc_simple functions in the SPL"
+ bool "Only use malloc_simple functions in the SPL"
help
Say Y here to only use the *_simple malloc functions from
malloc_simple.c, rather then using the versions from dlmalloc.c;
this will make the SPL binary smaller at the cost of more heap
usage as the *_simple malloc functions do not re-use free-ed mem.
-config TPL_SYS_MALLOC_SIMPLE
- bool
- prompt "Only use malloc_simple functions in the TPL"
- depends on TPL
+config SPL_SHARES_INIT_SP_ADDR
+ bool "SPL and U-Boot use the same initial stack pointer location"
+ depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK
+ default n if ARCH_SUNXI || ARCH_MX6 || ARCH_MX7
+ default y
help
- Say Y here to only use the *_simple malloc functions from
- malloc_simple.c, rather then using the versions from dlmalloc.c;
- this will make the TPL binary smaller at the cost of more heap
- usage as the *_simple malloc functions do not re-use free-ed mem.
+ In many cases, we can use the same initial stack pointer address for
+ both SPL and U-Boot itself. If you need to specify a different address
+ however, say N here and then set a different value in CONFIG_SPL_STACK.
+
+config SPL_STACK
+ hex "Initial stack pointer location"
+ depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && SPL_FRAMEWORK
+ depends on !SPL_SHARES_INIT_SP_ADDR
+ default 0x946bb8 if ARCH_MX7
+ default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB
+ default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
+ help
+ Address of the start of the stack SPL will use before SDRAM is
+ initialized.
config SPL_STACK_R
bool "Enable SDRAM location for SPL stack"
@@ -301,6 +361,23 @@
location is used. Normally we put the device tree at the end of BSS
but with this option enabled, it goes at _image_binary_end.
+config SYS_SPL_MALLOC
+ bool "Enable malloc pool in SPL"
+ depends on SPL_FRAMEWORK
+
+config HAS_CUSTOM_SPL_MALLOC_START
+ bool "For the SPL malloc pool, define a custom starting address"
+ depends on SYS_SPL_MALLOC
+
+config CUSTOM_SYS_SPL_MALLOC_ADDR
+ hex "SPL malloc addr"
+ depends on HAS_CUSTOM_SPL_MALLOC_START
+
+config SYS_SPL_MALLOC_SIZE
+ hex "Size of the SPL malloc pool"
+ depends on SYS_SPL_MALLOC
+ default 0x100000
+
config SPL_READ_ONLY
bool
depends on SPL_OF_PLATDATA
@@ -314,16 +391,6 @@
writeable memory) of anything it wants to modify, such as
device-private data.
-config TPL_SEPARATE_BSS
- bool "BSS section is in a different memory region from text"
- default y if SPL_SEPARATE_BSS
- help
- Some platforms need a large BSS region in TPL and can provide this
- because RAM is already set up. In this case BSS can be moved to RAM.
- This option should then be enabled so that the correct device tree
- location is used. Normally we put the device tree at the end of BSS
- but with this option enabled, it goes at _image_binary_end.
-
config SPL_BANNER_PRINT
bool "Enable output of the SPL banner 'U-Boot SPL ...'"
default y
@@ -332,15 +399,6 @@
info. Disabling this option could be useful to reduce SPL boot time
(e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
-config TPL_BANNER_PRINT
- bool "Enable output of the TPL banner 'U-Boot TPL ...'"
- depends on TPL
- default y
- help
- If this option is enabled, TPL will print the banner with version
- info. Disabling this option could be useful to reduce TPL boot time
- (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
-
config SPL_EARLY_BSS
depends on ARM && !ARM64
bool "Allows initializing BSS early before entering board_init_f"
@@ -591,6 +649,31 @@
filesystem from within SPL. Support for the underlying block
device (e.g. MMC or USB) must be enabled separately.
+config SPL_FS_LOAD_PAYLOAD_NAME
+ string "File to load for U-Boot from the filesystem"
+ depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS
+ default "tispl.bin" if SYS_K3_SPL_ATF
+ default "u-boot.itb" if SPL_LOAD_FIT
+ default "u-boot.img"
+ help
+ Filename to read to load U-Boot when reading from filesystem.
+
+config SPL_FS_LOAD_KERNEL_NAME
+ string "File to load for the OS kernel from the filesystem"
+ depends on (SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS) && SPL_OS_BOOT
+ default "uImage"
+ help
+ Filename to read to load for the OS kernel when reading from the
+ filesystem.
+
+config SPL_FS_LOAD_ARGS_NAME
+ string "File to load for the OS kernel argument parameters from the filesystem"
+ depends on (SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS) && SPL_OS_BOOT
+ default "args"
+ help
+ Filename to read to load for the OS kernel argument parameters from
+ the filesystem.
+
config SPL_FAT_WRITE
bool "Support write for FAT filesystems"
help
@@ -667,6 +750,7 @@
config SPL_DM_MAILBOX
bool "Support Mailbox"
+ depends on SPL_DM
help
Enable support for Mailbox within SPL. This enable the inter
processor communication protocols tobe used within SPL. Enable
@@ -749,13 +833,23 @@
This enables the drivers in drivers/mtd/nand/raw as part of an SPL
build.
+config SPL_NAND_RAW_ONLY
+ bool "Support to boot only raw u-boot.bin images"
+ depends on SPL_NAND_SUPPORT
+ help
+ Use this only if you need to save space.
+
config SPL_NAND_DRIVERS
bool "Use standard NAND driver"
help
SPL uses normal NAND drivers, not minimal drivers.
config SPL_NAND_ECC
- bool "Include standard software ECC in the SPL"
+ bool "Include standard ECC in SPL"
+
+config SPL_NAND_SOFTECC
+ bool "Use software ECC in SPL"
+ depends on SPL_NAND_ECC
config SPL_NAND_SIMPLE
bool "Support simple NAND drivers in SPL"
@@ -781,19 +875,9 @@
Enable support for loading payloads from UBI. See
README.ubispl for more info.
-if SPL_DM
-config SPL_DM_SPI
- bool "Support SPI DM drivers in SPL"
- help
- Enable support for SPI DM drivers in SPL.
+menu "UBI configuration for SPL"
+ depends on SPL_UBI
-config SPL_DM_SPI_FLASH
- bool "Support SPI DM FLASH drivers in SPL"
- help
- Enable support for SPI DM flash drivers in SPL.
-
-endif
-if SPL_UBI
config SPL_UBI_LOAD_BY_VOLNAME
bool "Support loading volumes by name"
help
@@ -803,58 +887,49 @@
config SPL_UBI_MAX_VOL_LEBS
int "Maximum number of LEBs per volume"
- depends on SPL_UBI
help
The maximum number of logical eraseblocks which a static volume
to load can contain. Used for sizing the scan data structure.
config SPL_UBI_MAX_PEB_SIZE
int "Maximum PEB size"
- depends on SPL_UBI
help
The maximum physical erase block size.
config SPL_UBI_MAX_PEBS
int "Maximum number of PEBs"
- depends on SPL_UBI
help
The maximum physical erase block size. If not overridden by
board code, this value will be used as the actual number of PEBs.
config SPL_UBI_PEB_OFFSET
int "Offset to first UBI PEB"
- depends on SPL_UBI
help
The offset in number of PEBs from the start of flash to the first
PEB part of the UBI image.
config SPL_UBI_VID_OFFSET
int "Offset to VID header"
- depends on SPL_UBI
config SPL_UBI_LEB_START
int "Offset to LEB in PEB"
- depends on SPL_UBI
help
The offset in bytes to the LEB within a PEB.
config SPL_UBI_INFO_ADDR
hex "Address to place UBI scan info"
- depends on SPL_UBI
help
Address for ubispl to place the scan info. Read README.ubispl to
determine the required size
config SPL_UBI_VOL_IDS
int "Maximum volume id"
- depends on SPL_UBI
help
The maximum volume id which can be loaded. Used for sizing the
scan data structure.
config SPL_UBI_LOAD_MONITOR_ID
int "id of U-Boot volume"
- depends on SPL_UBI
help
The UBI volume id from which to load U-Boot
@@ -866,13 +941,13 @@
config SPL_UBI_LOAD_KERNEL_ID
int "id of kernel volume"
- depends on SPL_OS_BOOT && SPL_UBI
+ depends on SPL_OS_BOOT
help
The UBI volume id from which to load the kernel
config SPL_UBI_LOAD_ARGS_ID
int "id of kernel args volume"
- depends on SPL_OS_BOOT && SPL_UBI
+ depends on SPL_OS_BOOT
help
The UBI volume id from which to load the device tree
@@ -882,7 +957,19 @@
Disable messages from UBI SPL. This leaves warnings
and errors enabled.
-endif # if SPL_UBI
+endmenu
+
+config SPL_DM_SPI
+ bool "Support SPI DM drivers in SPL"
+ depends on SPL_DM
+ help
+ Enable support for SPI DM drivers in SPL.
+
+config SPL_DM_SPI_FLASH
+ bool "Support SPI DM FLASH drivers in SPL"
+ depends on SPL_DM
+ help
+ Enable support for SPI DM flash drivers in SPL.
config SPL_NET
bool "Support networking"
@@ -893,19 +980,19 @@
the network stack uses a number of environment variables. See also
SPL_ETH.
-if SPL_NET
config SPL_NET_VCI_STRING
string "BOOTP Vendor Class Identifier string sent by SPL"
+ depends on SPL_NET
help
As defined by RFC 2132 the vendor class identifier field can be
sent by the client to identify the vendor type and configuration
of a client. This is often used in practice to allow for the DHCP
server to specify different files to load depending on if the ROM,
SPL or U-Boot itself makes the request
-endif # if SPL_NET
config SPL_NO_CPU_SUPPORT
- bool "Drop CPU code in SPL"
+ def_bool y
+ depends on (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
help
This is specific to the ARM926EJ-S CPU. It disables the standard
start.S start-up code, presumably so that a replacement can be
@@ -922,7 +1009,6 @@
config SPL_XIP_SUPPORT
bool "Support XIP"
- depends on SPL
help
Enable support for execute in place of U-Boot or kernel image. There
is no need to copy image from flash to ram if flash supports execute
@@ -944,16 +1030,25 @@
Enable booting directly to an OS from SPL.
for more info read doc/README.falcon
-if SPL_OS_BOOT
+config SYS_SPL_ARGS_ADDR
+ hex "Address in memory to load 'args' file for Falcon Mode to"
+ depends on SPL_OS_BOOT
+ default 0x88000000 if ARCH_OMAP2PLUS
+ help
+ Address in memory where the 'args' file, typically a device tree
+ will be loaded in to memory.
+
+config SYS_NAND_SPL_KERNEL_OFFS
+ hex "Address in memory to load the OS file for Falcon mode to"
+ depends on SPL_OS_BOOT && SPL_NAND_SUPPORT
+
config SYS_OS_BASE
hex "addr, where OS is found"
- depends on SPL_NOR_SUPPORT
+ depends on SPL_OS_BOOT && SPL_NOR_SUPPORT
help
Specify the address, where the OS image is found, which
gets booted.
-endif # SPL_OS_BOOT
-
config SPL_FALCON_BOOT_MMCSD
bool "Enable Falcon boot from MMC or SD media"
depends on SPL_OS_BOOT && SPL_MMC
@@ -970,6 +1065,20 @@
Note that the Falcon mode image can also be a FIT, if FIT support is
enabled.
+config SYS_MMCSD_RAW_MODE_ARGS_SECTOR
+ hex "Falcon mode: Sector to load 'args' from MMC"
+ depends on SPL_FALCON_BOOT_MMCSD
+ help
+ When Falcon mode is used with an MMC or SD media, SPL needs to know
+ where to look for the OS 'args', typically a device tree. The
+ contents are expected to begin at the raw MMC specified in this config.
+ Note that if using a FIT image, this and the next option can be set to
+ 0x0.
+
+config SYS_MMCSD_RAW_MODE_ARGS_SECTORS
+ hex "Falcon mode: Number of sectors to load for 'args' from MMC"
+ depends on SPL_FALCON_BOOT_MMCSD && SYS_MMCSD_RAW_MODE_ARGS_SECTOR != 0x0
+
config SPL_PAYLOAD
string "SPL payload"
default "tpl/u-boot-with-tpl.bin" if TPL
@@ -1007,7 +1116,7 @@
config SPL_DM_RESET
bool "Support reset drivers"
- depends on SPL
+ depends on SPL_DM
help
Enable support for reset control in SPL.
That can be useful in SPL to handle IP reset in driver, as in U-Boot,
@@ -1310,6 +1419,7 @@
config SPL_AM33XX_ENABLE_RTC32K_OSC
bool "Enable the RTC32K OSC on AM33xx based platforms"
+ depends on AM33XX
default y if AM33XX
help
Enable access to the AM33xx RTC and select the external 32kHz clock
@@ -1339,519 +1449,15 @@
help
Load address of the OpenSBI binary.
-config TPL
- bool
- depends on SUPPORT_TPL
- prompt "Enable TPL"
+config SPL_TARGET
+ string "Addtional build targets for 'make'"
+ default "spl/u-boot-spl.srec" if RCAR_GEN2
+ default "spl/u-boot-spl.scif" if RCAR_GEN3
+ default ""
help
- If you want to build TPL as well as the normal image and SPL, say Y.
-
-if TPL
-
-config TPL_SIZE_LIMIT
- hex "Maximum size of TPL image"
- depends on TPL
- default 0x0
- help
- Specifies the maximum length of the U-Boot TPL image.
- If this value is zero, it is ignored.
-
-config TPL_BINMAN_SYMBOLS
- bool "Declare binman symbols in TPL"
- depends on SPL_FRAMEWORK && BINMAN
- default y
- help
- This enables use of symbols in TPL which refer to U-Boot, enabling TPL
- to obtain the location of U-Boot simply by calling spl_get_image_pos()
- and spl_get_image_size().
-
- For this to work, you must have a U-Boot image in the binman image, so
- binman can update TPL with the location of it.
-
-config TPL_FRAMEWORK
- bool "Support TPL based upon the common SPL framework"
- default y if SPL_FRAMEWORK
- help
- Enable the SPL framework under common/spl/ for TPL builds.
- This framework supports MMC, NAND and YMODEM and other methods
- loading of U-Boot's SPL stage. If unsure, say Y.
-
-config TPL_HANDOFF
- bool "Pass hand-off information from TPL to SPL and U-Boot proper"
- depends on HANDOFF && TPL_BLOBLIST
- default y
- help
- This option enables TPL to write handoff information. This can be
- used to pass information like the size of SDRAM from TPL to U-Boot
- proper. The information is also available to SPL if it is useful
- there.
-
-config TPL_BOARD_INIT
- bool "Call board-specific initialization in TPL"
- help
- If this option is enabled, U-Boot will call the function
- spl_board_init() from board_init_r(). This function should be
- provided by the board.
-
-config TPL_BOOTCOUNT_LIMIT
- bool "Support bootcount in TPL"
- depends on TPL_ENV_SUPPORT
- help
- If this option is enabled, the TPL will support bootcount.
- For example, it may be useful to choose the device to boot.
-
-config TPL_LDSCRIPT
- string "Linker script for the TPL stage"
- depends on TPL
- default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
- default "arch/\$(ARCH)/cpu/u-boot-spl.lds"
- help
- The TPL stage will usually require a different linker-script
- (as it runs from a different memory region) than the regular
- U-Boot stage. Set this to the path of the linker-script to
- be used for TPL.
-
- May be left empty to trigger the Makefile infrastructure to
- fall back to the linker-script used for the SPL stage.
-
-config TPL_NEEDS_SEPARATE_STACK
- bool "TPL needs a separate initial stack-pointer"
- depends on TPL
- help
- Enable, if the TPL stage should not inherit its initial
- stack-pointer from the settings for the SPL stage.
-
-config TPL_POWER
- bool "Support power drivers"
- help
- Enable support for power control in TPL. This includes support
- for PMICs (Power-management Integrated Circuits) and some of the
- features provided by PMICs. In particular, voltage regulators can
- be used to enable/disable power and vary its voltage. That can be
- useful in TPL to turn on boot peripherals and adjust CPU voltage
- so that the clock speed can be increased. This enables the drivers
- in drivers/power, drivers/power/pmic and drivers/power/regulator
- as part of an TPL build.
-
-config TPL_TEXT_BASE
- hex "Base address for the .text section of the TPL stage"
- default 0
- help
- The base address for the .text section of the TPL stage.
-
-config TPL_MAX_SIZE
- int "Maximum size (in bytes) for the TPL stage"
- default 0
- depends on TPL
- help
- The maximum size (in bytes) of the TPL stage.
-
-config TPL_STACK
- hex "Address of the initial stack-pointer for the TPL stage"
- depends on TPL_NEEDS_SEPARATE_STACK
- help
- The address of the initial stack-pointer for the TPL stage.
- Usually this will be the (aligned) top-of-stack.
-
-config TPL_READ_ONLY
- bool
- depends on TPL_OF_PLATDATA
- select TPL_OF_PLATDATA_NO_BIND
- select TPL_OF_PLATDATA_RT
- help
- Some platforms (e.g. x86 Apollo Lake) load SPL into a read-only
- section of memory. This means that of-platdata must make a copy (in
- writeable memory) of anything it wants to modify, such as
- device-private data.
-
-config TPL_BOOTROM_SUPPORT
- bool "Support returning to the BOOTROM (from TPL)"
- help
- Some platforms (e.g. the Rockchip RK3368) provide support in their
- ROM for loading the next boot-stage after performing basic setup
- from the TPL stage.
-
- Enable this option, to return to the BOOTROM through the
- BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
- boot device list, if not implemented for a given board)
-
-config TPL_CRC32
- bool "Support CRC32 in TPL"
- default y if TPL_ENV_SUPPORT || TPL_BLOBLIST
- help
- Enable this to support CRC32 in uImages or FIT images within SPL.
- This is a 32-bit checksum value that can be used to verify images.
- For FIT images, this is the least secure type of checksum, suitable
- for detected accidental image corruption. For secure applications you
- should consider SHA1 or SHA256.
-
-config TPL_DRIVERS_MISC
- bool "Support misc drivers in TPL"
- help
- Enable miscellaneous drivers in TPL. These drivers perform various
- tasks that don't fall nicely into other categories, Enable this
- option to build the drivers in drivers/misc as part of an TPL
- build, for those that support building in TPL (not all drivers do).
-
-config TPL_ENV_SUPPORT
- bool "Support an environment"
- help
- Enable environment support in TPL. See SPL_ENV_SUPPORT for details.
-
-config TPL_GPIO
- bool "Support GPIO in TPL"
- help
- Enable support for GPIOs (General-purpose Input/Output) in TPL.
- GPIOs allow U-Boot to read the state of an input line (high or
- low) and set the state of an output line. This can be used to
- drive LEDs, control power to various system parts and read user
- input. GPIOs can be useful in TPL to enable a 'sign-of-life' LED,
- for example. Enable this option to build the drivers in
- drivers/gpio as part of an TPL build.
-
-config TPL_I2C
- bool "Support I2C"
- help
- Enable support for the I2C bus in TPL. See SPL_I2C for
- details.
-
-config TPL_LIBCOMMON_SUPPORT
- bool "Support common libraries"
- help
- Enable support for common U-Boot libraries within TPL. See
- SPL_LIBCOMMON_SUPPORT for details.
-
-config TPL_LIBGENERIC_SUPPORT
- bool "Support generic libraries"
- help
- Enable support for generic U-Boot libraries within TPL. See
- SPL_LIBGENERIC_SUPPORT for details.
-
-config TPL_MPC8XXX_INIT_DDR
- bool "Support MPC8XXX DDR init"
- help
- Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See
- SPL_MPC8XXX_INIT_DDR for details.
-
-config TPL_MMC
- bool "Support MMC"
- depends on MMC
- help
- Enable support for MMC within TPL. See SPL_MMC for details.
-
-config TPL_NAND_SUPPORT
- bool "Support NAND flash"
- help
- Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details.
-
-config TPL_PCI
- bool "Support PCI drivers"
- help
- Enable support for PCI in TPL. For platforms that need PCI to boot,
- or must perform some init using PCI in SPL, this provides the
- necessary driver support. This enables the drivers in drivers/pci
- as part of a TPL build.
-
-config TPL_PCH
- bool "Support PCH drivers"
- help
- Enable support for PCH (Platform Controller Hub) devices in TPL.
- These are used to set up GPIOs and the SPI peripheral early in
- boot. This enables the drivers in drivers/pch as part of a TPL
- build.
-
-config TPL_RAM_SUPPORT
- bool "Support booting from RAM"
- help
- Enable booting of an image in RAM. The image can be preloaded or
- it can be loaded by TPL directly into RAM (e.g. using USB).
-
-config TPL_RAM_DEVICE
- bool "Support booting from preloaded image in RAM"
- depends on TPL_RAM_SUPPORT
- help
- Enable booting of an image already loaded in RAM. The image has to
- be already in memory when TPL takes over, e.g. loaded by the boot
- ROM.
-
-config TPL_RTC
- bool "Support RTC drivers"
- help
- Enable RTC (Real-time Clock) support in TPL. This includes support
- for reading and setting the time. Some RTC devices also have some
- non-volatile (battery-backed) memory which is accessible if
- needed. This enables the drivers in drivers/rtc as part of an TPL
- build.
-
-config TPL_SERIAL
- bool "Support serial"
- select TPL_PRINTF
- select TPL_STRTO
- help
- Enable support for serial in TPL. See SPL_SERIAL for
- details.
-
-config TPL_SPI_FLASH_SUPPORT
- bool "Support SPI flash drivers"
- help
- Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT
- for details.
-
-config TPL_SPI_FLASH_TINY
- bool "Enable low footprint TPL SPI Flash support"
- depends on TPL_SPI_FLASH_SUPPORT && !SPI_FLASH_BAR
- default y if SPI_FLASH
- help
- Enable lightweight TPL SPI Flash support that supports just reading
- data/images from flash. No support to write/erase flash. Enable
- this if you have TPL size limitations and don't need full-fledged
- SPI flash support.
-
-config TPL_SPI_LOAD
- bool "Support loading from SPI flash"
- depends on TPL_SPI_FLASH_SUPPORT
- help
- Enable support for loading next stage, U-Boot or otherwise, from
- SPI NOR in U-Boot TPL.
-
-config TPL_SPI
- bool "Support SPI drivers"
- help
- Enable support for using SPI in TPL. See SPL_SPI for
- details.
-
-config TPL_DM_SPI
- bool "Support SPI DM drivers in TPL"
- help
- Enable support for SPI DM drivers in TPL.
-
-config TPL_DM_SPI_FLASH
- bool "Support SPI DM FLASH drivers in TPL"
- help
- Enable support for SPI DM flash drivers in TPL.
-
-config TPL_YMODEM_SUPPORT
- bool "Support loading using Ymodem"
- depends on TPL_SERIAL
- help
- While loading from serial is slow it can be a useful backup when
- there is no other option. The Ymodem protocol provides a reliable
- means of transmitting U-Boot over a serial line for using in TPL,
- with a checksum to ensure correctness.
-
-endif # TPL
-
-config VPL
- bool
- depends on SUPPORT_SPL
- prompt "Enable VPL"
- help
- If you want to build VPL as well as the normal image, TPL and SPL,
- say Y.
-
-if VPL
-
-config VPL_BANNER_PRINT
- bool "Enable output of the VPL banner 'U-Boot VPL ...'"
- depends on VPL
- default y
- help
- If this option is enabled, VPL will print the banner with version
- info. Disabling this option could be useful to reduce VPL boot time
- (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
-
-config VPL_BOARD_INIT
- bool "Call board-specific initialization in VPL"
- help
- If this option is enabled, U-Boot will call the function
- spl_board_init() from board_init_r(). This function should be
- provided by the board.
-
-config VPL_CACHE
- depends on CACHE
- bool "Support cache drivers in VPL"
- help
- Enable support for cache drivers in VPL.
-
-config VPL_CRC32
- bool "Support CRC32 in VPL"
- default y if VPL_ENV_SUPPORT || VPL_BLOBLIST
- help
- Enable this to support CRC32 in uImages or FIT images within VPL.
- This is a 32-bit checksum value that can be used to verify images.
- For FIT images, this is the least secure type of checksum, suitable
- for detected accidental image corruption. For secure applications you
- should consider SHA1 or SHA256.
-
-config VPL_DM_SPI
- bool "Support SPI DM drivers in VPL"
- help
- Enable support for SPI DM drivers in VPL.
-
-config VPL_DM_SPI_FLASH
- bool "Support SPI DM FLASH drivers in VPL"
- help
- Enable support for SPI DM flash drivers in VPL.
-
-config VPL_FRAMEWORK
- bool "Support VPL based upon the common SPL framework"
- default y
- help
- Enable the SPL framework under common/spl/ for VPL builds.
- This framework supports MMC, NAND and YMODEM and other methods
- loading of U-Boot's next stage. If unsure, say Y.
-
-config VPL_HANDOFF
- bool "Pass hand-off information from VPL to SPL"
- depends on HANDOFF && VPL_BLOBLIST
- default y
- help
- This option enables VPL to write handoff information. This can be
- used to pass information like the size of SDRAM from VPL to SPL. Also
- VPL can receive information from TPL in the same place if that is
- enabled.
-
-config VPL_LIBCOMMON_SUPPORT
- bool "Support common libraries"
- default y if SPL_LIBCOMMON_SUPPORT
- help
- Enable support for common U-Boot libraries within VPL. See
- SPL_LIBCOMMON_SUPPORT for details.
-
-config VPL_LIBGENERIC_SUPPORT
- bool "Support generic libraries"
- default y if SPL_LIBGENERIC_SUPPORT
- help
- Enable support for generic U-Boot libraries within VPL. These
- libraries include generic code to deal with device tree, hashing,
- printf(), compression and the like. This option is enabled on many
- boards. Enable this option to build the code in lib/ as part of a
- VPL build.
-
-config VPL_DRIVERS_MISC
- bool "Support misc drivers"
- default y if TPL_DRIVERS_MISC
- help
- Enable miscellaneous drivers in VPL. These drivers perform various
- tasks that don't fall nicely into other categories, Enable this
- option to build the drivers in drivers/misc as part of a VPL
- build, for those that support building in VPL (not all drivers do).
-
-config VPL_ENV_SUPPORT
- bool "Support an environment"
- help
- Enable environment support in VPL. The U-Boot environment provides
- a number of settings (essentially name/value pairs) which can
- control many aspects of U-Boot's operation. Enabling this option will
- make env_get() and env_set() available in VSPL.
-
-config VPL_GPIO
- bool "Support GPIO in VPL"
- default y if SPL_GPIO
- help
- Enable support for GPIOs (General-purpose Input/Output) in VPL.
- GPIOs allow U-Boot to read the state of an input line (high or
- low) and set the state of an output line. This can be used to
- drive LEDs, control power to various system parts and read user
- input. GPIOs can be useful in VPL to enable a 'sign-of-life' LED,
- for example. Enable this option to build the drivers in
- drivers/gpio as part of a VPL build.
-
-config VPL_HANDOFF
- bool "Pass hand-off information from VPL to SPL and U-Boot proper"
- depends on HANDOFF && VPL_BLOBLIST
- default y
- help
- This option enables VPL to write handoff information. This can be
- used to pass information like the size of SDRAM from VPL to U-Boot
- proper. The information is also available to VPL if it is useful
- there.
-
-config VPL_HASH
- bool "Support hashing drivers in VPL"
- depends on VPL
- select SHA1
- select SHA256
- help
- Enable hashing drivers in VPL. These drivers can be used to
- accelerate secure boot processing in secure applications. Enable
- this option to build system-specific drivers for hash acceleration
- as part of a VPL build.
-
-config VPL_I2C_SUPPORT
- bool "Support I2C in VPL"
- default y if SPL_I2C_SUPPORT
- help
- Enable support for the I2C bus in VPL. Vee SPL_I2C_SUPPORT for
- details.
-
-config VPL_PCH_SUPPORT
- bool "Support PCH drivers"
- default y if TPL_PCH_SUPPORT
- help
- Enable support for PCH (Platform Controller Hub) devices in VPL.
- These are used to set up GPIOs and the SPI peripheral early in
- boot. This enables the drivers in drivers/pch as part of a VPL
- build.
-
-config VPL_PCI
- bool "Support PCI drivers"
- default y if SPL_PCI
- help
- Enable support for PCI in VPL. For platforms that need PCI to boot,
- or must perform some init using PCI in VPL, this provides the
- necessary driver support. This enables the drivers in drivers/pci
- as part of a VPL build.
-
-config VPL_RTC
- bool "Support RTC drivers"
- help
- Enable RTC (Real-time Clock) support in VPL. This includes support
- for reading and setting the time. Some RTC devices also have some
- non-volatile (battery-backed) memory which is accessible if
- needed. This enables the drivers in drivers/rtc as part of a VPL
- build.
-
-config VPL_SERIAL
- bool "Support serial"
- default y if TPL_SERIAL
- select VPL_PRINTF
- select VPL_STRTO
- help
- Enable support for serial in VPL. See SPL_SERIAL_SUPPORT for
- details.
-
-config VPL_SIZE_LIMIT
- hex "Maximum size of VPL image"
- depends on VPL
- default 0x0
- help
- Specifies the maximum length of the U-Boot VPL image.
- If this value is zero, it is ignored.
-
-config VPL_SPI
- bool "Support SPI drivers"
- help
- Enable support for using SPI in VPL. See SPL_SPI_SUPPORT for
- details.
-
-config VPL_SPI_FLASH_SUPPORT
- bool "Support SPI flash drivers"
- help
- Enable support for using SPI flash in VPL, and loading U-Boot from
- SPI flash. SPI flash (Serial Peripheral Bus flash) is named after
- the SPI bus that is used to connect it to a system. It is a simple
- but fast bidirectional 4-wire bus (clock, chip select and two data
- lines). This enables the drivers in drivers/mtd/spi as part of a
- VPL build. This normally requires VPL_SPI_SUPPORT.
-
-config VPL_TEXT_BASE
- hex "VPL Text Base"
- default 0x0
- help
- The address in memory that VPL will be running from.
+ On some platforms we need to have 'make' run additional build target
+ rules. If required on your platform, enter it here, otherwise leave blank.
-endif # VPL
config SPL_AT91_MCK_BYPASS
bool "Use external clock signal as a source of main clock for AT91 platforms"
@@ -1863,6 +1469,21 @@
The external source has to provide a stable clock on the XIN pin.
If this option is disabled, the SoC expects a crystal oscillator
that needs driving on both XIN and XOUT lines.
-
-endif # SPL
endmenu
+
+config TPL
+ depends on SUPPORT_TPL
+ bool "Enable TPL"
+ help
+ If you want to build TPL as well as the normal image and SPL, say Y.
+
+source "common/spl/Kconfig.tpl"
+
+config VPL
+ depends on SUPPORT_SPL
+ bool "Enable VPL"
+ help
+ If you want to build VPL as well as the normal image, TPL and SPL,
+ say Y.
+
+source "common/spl/Kconfig.vpl"
diff --git a/common/spl/Kconfig.nxp b/common/spl/Kconfig.nxp
new file mode 100644
index 0000000..8da8553
--- /dev/null
+++ b/common/spl/Kconfig.nxp
@@ -0,0 +1,124 @@
+menu "PowerPC and LayerScape SPL Boot options"
+ depends on (PPC && SUPPORT_SPL && !SPL_FRAMEWORK) || \
+ ((ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && SUPPORT_SPL)
+
+config SPL_NAND_BOOT
+ bool "Load SPL from NAND flash"
+ depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
+
+config SPL_MMC_BOOT
+ bool "Load SPL from SD Card / eMMC"
+ depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
+
+config SPL_SPI_BOOT
+ bool "Load SPL from SPI flash"
+ depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
+
+config SPL_FSL_PBL
+ bool "Create SPL in Freescale PBI format"
+ depends on (PPC || ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) && \
+ SUPPORT_SPL
+ help
+ Create boot binary having SPL binary in PBI format concatenated with
+ u-boot binary.
+
+config SPL_SYS_CCSR_DO_NOT_RELOCATE
+ bool "Ensures that CCSR is not relocated"
+ depends on PPC
+ help
+ If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a
+ value that ensures that CCSR is not relocated.
+
+config TPL_SYS_CCSR_DO_NOT_RELOCATE
+ def_bool y
+ depends on SPL_SYS_CCSR_DO_NOT_RELOCATE
+
+menu "PowerPC SPL / TPL specific options"
+ depends on PPC && (SPL && !SPL_FRAMEWORK)
+
+config SPL_INIT_MINIMAL
+ bool "Arch init code will be built for a very small image"
+
+config SPL_FLUSH_IMAGE
+ bool "Clean dcache and invalidate icache after loading the image"
+
+config SPL_SKIP_RELOCATE
+ bool "Skip relocating SPL"
+
+config SPL_GD_ADDR
+ hex "Address to use for global data (gd) in SPL"
+ depends on !SPL_INIT_MINIMAL
+
+config SPL_RELOC_TEXT_BASE
+ hex "Address to relocate SPL to"
+ default SPL_TEXT_BASE
+ help
+ If unspecified, this is equal to CONFIG_SPL_TEXT_BASE (i.e. no
+ relocation is done).
+
+config SPL_RELOC_STACK
+ hex "Address of the start of the stack SPL will use after relocation."
+ help
+ If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START. Starting
+ address of the malloc pool used in SPL. When this option is set the full
+ malloc is used in SPL and it is set up by spl_init() and before that, the
+ simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined.
+
+config SPL_RELOC_MALLOC
+ bool "SPL has malloc pool after relocation"
+
+config SPL_RELOC_MALLOC_ADDR
+ hex "Address of malloc pool in SPL"
+ depends on SPL_RELOC_MALLOC
+
+config SPL_RELOC_MALLOC_SIZE
+ hex "Size of malloc pool in SPL"
+ depends on SPL_RELOC_MALLOC
+
+config TPL_GD_ADDR
+ hex "Address to use for global data (gd) in TPL"
+ depends on TPL
+
+config TPL_RELOC_TEXT_BASE
+ hex "Address to relocate TPL to"
+ depends on TPL
+ default TPL_TEXT_BASE
+ help
+ If unspecified, this is equal to CONFIG_TPL_TEXT_BASE (i.e. no
+ relocation is done).
+
+config TPL_RELOC_STACK
+ hex "Address of the start of the stack TPL will use after relocation."
+ depends on TPL
+ help
+ If unspecified, this is equal to CONFIG_SYS_TPL_MALLOC_START. Starting
+ address of the malloc pool used in TPL. When this option is set the full
+ malloc is used in TPL and it is set up by spl_init() and before that, the
+ simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined.
+
+config TPL_RELOC_MALLOC
+ bool "TPL has malloc pool after relocation"
+ depends on TPL
+
+config TPL_RELOC_MALLOC_ADDR
+ hex "Address of malloc pool in TPL"
+ depends on TPL_RELOC_MALLOC
+
+config TPL_RELOC_MALLOC_SIZE
+ hex "Size of malloc pool in TPL"
+ depends on TPL_RELOC_MALLOC
+
+config TPL_PAD_TO
+ hex "Offset to which the TPL should be padded before appending the TPL payload"
+ depends on TPL && !TPL_FRAMEWORK
+ default TPL_MAX_SIZE
+ help
+ Image offset to which the TPL should be padded before appending the
+ TPL payload. By default, this is defined as CONFIG_TPL_MAX_SIZE, or 0 if
+ CONFIG_TPL_MAX_SIZE is undefined. CONFIG_TPL_PAD_TO must be either
+ 0, meaning to append the TPL payload without any padding, or >=
+ CONFIG_TPL_MAX_SIZE.
+endmenu
+
+endmenu
+
diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl
new file mode 100644
index 0000000..9a0e719
--- /dev/null
+++ b/common/spl/Kconfig.tpl
@@ -0,0 +1,322 @@
+menu "TPL configuration options"
+ depends on TPL
+
+config TPL_SIZE_LIMIT
+ hex "Maximum size of TPL image"
+ default 0x0
+ help
+ Specifies the maximum length of the U-Boot TPL image.
+ If this value is zero, it is ignored.
+
+config TPL_BINMAN_SYMBOLS
+ bool "Declare binman symbols in TPL"
+ depends on SPL_FRAMEWORK && BINMAN
+ default y
+ help
+ This enables use of symbols in TPL which refer to U-Boot, enabling TPL
+ to obtain the location of U-Boot simply by calling spl_get_image_pos()
+ and spl_get_image_size().
+
+ For this to work, you must have a U-Boot image in the binman image, so
+ binman can update TPL with the location of it.
+
+config TPL_FRAMEWORK
+ bool "Support TPL based upon the common SPL framework"
+ default y if SPL_FRAMEWORK
+ help
+ Enable the SPL framework under common/spl/ for TPL builds.
+ This framework supports MMC, NAND and YMODEM and other methods
+ loading of U-Boot's SPL stage. If unsure, say Y.
+
+config TPL_BANNER_PRINT
+ bool "Enable output of the TPL banner 'U-Boot TPL ...'"
+ default y
+ help
+ If this option is enabled, TPL will print the banner with version
+ info. Disabling this option could be useful to reduce TPL boot time
+ (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
+
+config TPL_HANDOFF
+ bool "Pass hand-off information from TPL to SPL and U-Boot proper"
+ depends on HANDOFF && TPL_BLOBLIST
+ default y
+ help
+ This option enables TPL to write handoff information. This can be
+ used to pass information like the size of SDRAM from TPL to U-Boot
+ proper. The information is also available to SPL if it is useful
+ there.
+
+config TPL_BOARD_INIT
+ bool "Call board-specific initialization in TPL"
+ help
+ If this option is enabled, U-Boot will call the function
+ spl_board_init() from board_init_r(). This function should be
+ provided by the board.
+
+config TPL_BOOTCOUNT_LIMIT
+ bool "Support bootcount in TPL"
+ depends on TPL_ENV_SUPPORT
+ help
+ If this option is enabled, the TPL will support bootcount.
+ For example, it may be useful to choose the device to boot.
+
+config TPL_SYS_MALLOC_SIMPLE
+ bool
+ prompt "Only use malloc_simple functions in the TPL"
+ help
+ Say Y here to only use the *_simple malloc functions from
+ malloc_simple.c, rather then using the versions from dlmalloc.c;
+ this will make the TPL binary smaller at the cost of more heap
+ usage as the *_simple malloc functions do not re-use free-ed mem.
+
+config TPL_SEPARATE_BSS
+ bool "BSS section is in a different memory region from text"
+ default y if SPL_SEPARATE_BSS
+ help
+ Some platforms need a large BSS region in TPL and can provide this
+ because RAM is already set up. In this case BSS can be moved to RAM.
+ This option should then be enabled so that the correct device tree
+ location is used. Normally we put the device tree at the end of BSS
+ but with this option enabled, it goes at _image_binary_end.
+
+config TPL_LDSCRIPT
+ string "Linker script for the TPL stage"
+ default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
+ default "arch/\$(ARCH)/cpu/u-boot-spl.lds"
+ help
+ The TPL stage will usually require a different linker-script
+ (as it runs from a different memory region) than the regular
+ U-Boot stage. Set this to the path of the linker-script to
+ be used for TPL.
+
+ May be left empty to trigger the Makefile infrastructure to
+ fall back to the linker-script used for the SPL stage.
+
+config TPL_NEEDS_SEPARATE_STACK
+ bool "TPL needs a separate initial stack-pointer"
+ help
+ Enable, if the TPL stage should not inherit its initial
+ stack-pointer from the settings for the SPL stage.
+
+config TPL_POWER
+ bool "Support power drivers"
+ help
+ Enable support for power control in TPL. This includes support
+ for PMICs (Power-management Integrated Circuits) and some of the
+ features provided by PMICs. In particular, voltage regulators can
+ be used to enable/disable power and vary its voltage. That can be
+ useful in TPL to turn on boot peripherals and adjust CPU voltage
+ so that the clock speed can be increased. This enables the drivers
+ in drivers/power, drivers/power/pmic and drivers/power/regulator
+ as part of an TPL build.
+
+config TPL_TEXT_BASE
+ hex "Base address for the .text section of the TPL stage"
+ default 0
+ help
+ The base address for the .text section of the TPL stage.
+
+config TPL_MAX_SIZE
+ hex "Maximum size (in bytes) for the TPL stage"
+ default 0x2e000 if ROCKCHIP_RK3399
+ default 0x8000 if ROCKCHIP_RK3288
+ default 0x7000 if ROCKCHIP_RK322X || ROCKCHIP_RK3328 || ROCKCHIP_RK3368
+ default 0x2800 if ROCKCHIP_PX30
+ default 0x0
+ help
+ The maximum size (in bytes) of the TPL stage.
+
+config TPL_STACK
+ hex "Address of the initial stack-pointer for the TPL stage"
+ depends on TPL_NEEDS_SEPARATE_STACK
+ help
+ The address of the initial stack-pointer for the TPL stage.
+ Usually this will be the (aligned) top-of-stack.
+
+config TPL_READ_ONLY
+ bool
+ depends on TPL_OF_PLATDATA
+ select TPL_OF_PLATDATA_NO_BIND
+ select TPL_OF_PLATDATA_RT
+ help
+ Some platforms (e.g. x86 Apollo Lake) load SPL into a read-only
+ section of memory. This means that of-platdata must make a copy (in
+ writeable memory) of anything it wants to modify, such as
+ device-private data.
+
+config TPL_BOOTROM_SUPPORT
+ bool "Support returning to the BOOTROM (from TPL)"
+ help
+ Some platforms (e.g. the Rockchip RK3368) provide support in their
+ ROM for loading the next boot-stage after performing basic setup
+ from the TPL stage.
+
+ Enable this option, to return to the BOOTROM through the
+ BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
+ boot device list, if not implemented for a given board)
+
+config TPL_CRC32
+ bool "Support CRC32 in TPL"
+ default y if TPL_ENV_SUPPORT || TPL_BLOBLIST
+ help
+ Enable this to support CRC32 in uImages or FIT images within SPL.
+ This is a 32-bit checksum value that can be used to verify images.
+ For FIT images, this is the least secure type of checksum, suitable
+ for detected accidental image corruption. For secure applications you
+ should consider SHA1 or SHA256.
+
+config TPL_DRIVERS_MISC
+ bool "Support misc drivers in TPL"
+ help
+ Enable miscellaneous drivers in TPL. These drivers perform various
+ tasks that don't fall nicely into other categories, Enable this
+ option to build the drivers in drivers/misc as part of an TPL
+ build, for those that support building in TPL (not all drivers do).
+
+config TPL_ENV_SUPPORT
+ bool "Support an environment"
+ help
+ Enable environment support in TPL. See SPL_ENV_SUPPORT for details.
+
+config TPL_GPIO
+ bool "Support GPIO in TPL"
+ help
+ Enable support for GPIOs (General-purpose Input/Output) in TPL.
+ GPIOs allow U-Boot to read the state of an input line (high or
+ low) and set the state of an output line. This can be used to
+ drive LEDs, control power to various system parts and read user
+ input. GPIOs can be useful in TPL to enable a 'sign-of-life' LED,
+ for example. Enable this option to build the drivers in
+ drivers/gpio as part of an TPL build.
+
+config TPL_I2C
+ bool "Support I2C"
+ help
+ Enable support for the I2C bus in TPL. See SPL_I2C for
+ details.
+
+config TPL_LIBCOMMON_SUPPORT
+ bool "Support common libraries"
+ help
+ Enable support for common U-Boot libraries within TPL. See
+ SPL_LIBCOMMON_SUPPORT for details.
+
+config TPL_LIBGENERIC_SUPPORT
+ bool "Support generic libraries"
+ help
+ Enable support for generic U-Boot libraries within TPL. See
+ SPL_LIBGENERIC_SUPPORT for details.
+
+config TPL_MPC8XXX_INIT_DDR
+ bool "Support MPC8XXX DDR init"
+ help
+ Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See
+ SPL_MPC8XXX_INIT_DDR for details.
+
+config TPL_MMC
+ bool "Support MMC"
+ depends on MMC
+ help
+ Enable support for MMC within TPL. See SPL_MMC for details.
+
+config TPL_NAND_SUPPORT
+ bool "Support NAND flash"
+ help
+ Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details.
+
+config TPL_PCI
+ bool "Support PCI drivers"
+ help
+ Enable support for PCI in TPL. For platforms that need PCI to boot,
+ or must perform some init using PCI in SPL, this provides the
+ necessary driver support. This enables the drivers in drivers/pci
+ as part of a TPL build.
+
+config TPL_PCH
+ bool "Support PCH drivers"
+ help
+ Enable support for PCH (Platform Controller Hub) devices in TPL.
+ These are used to set up GPIOs and the SPI peripheral early in
+ boot. This enables the drivers in drivers/pch as part of a TPL
+ build.
+
+config TPL_RAM_SUPPORT
+ bool "Support booting from RAM"
+ help
+ Enable booting of an image in RAM. The image can be preloaded or
+ it can be loaded by TPL directly into RAM (e.g. using USB).
+
+config TPL_RAM_DEVICE
+ bool "Support booting from preloaded image in RAM"
+ depends on TPL_RAM_SUPPORT
+ help
+ Enable booting of an image already loaded in RAM. The image has to
+ be already in memory when TPL takes over, e.g. loaded by the boot
+ ROM.
+
+config TPL_RTC
+ bool "Support RTC drivers"
+ help
+ Enable RTC (Real-time Clock) support in TPL. This includes support
+ for reading and setting the time. Some RTC devices also have some
+ non-volatile (battery-backed) memory which is accessible if
+ needed. This enables the drivers in drivers/rtc as part of an TPL
+ build.
+
+config TPL_SERIAL
+ bool "Support serial"
+ select TPL_PRINTF
+ select TPL_STRTO
+ help
+ Enable support for serial in TPL. See SPL_SERIAL for
+ details.
+
+config TPL_SPI_FLASH_SUPPORT
+ bool "Support SPI flash drivers"
+ help
+ Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT
+ for details.
+
+config TPL_SPI_FLASH_TINY
+ bool "Enable low footprint TPL SPI Flash support"
+ depends on TPL_SPI_FLASH_SUPPORT && !SPI_FLASH_BAR
+ default y if SPI_FLASH
+ help
+ Enable lightweight TPL SPI Flash support that supports just reading
+ data/images from flash. No support to write/erase flash. Enable
+ this if you have TPL size limitations and don't need full-fledged
+ SPI flash support.
+
+config TPL_SPI_LOAD
+ bool "Support loading from SPI flash"
+ depends on TPL_SPI_FLASH_SUPPORT
+ help
+ Enable support for loading next stage, U-Boot or otherwise, from
+ SPI NOR in U-Boot TPL.
+
+config TPL_SPI
+ bool "Support SPI drivers"
+ help
+ Enable support for using SPI in TPL. See SPL_SPI for
+ details.
+
+config TPL_DM_SPI
+ bool "Support SPI DM drivers in TPL"
+ help
+ Enable support for SPI DM drivers in TPL.
+
+config TPL_DM_SPI_FLASH
+ bool "Support SPI DM FLASH drivers in TPL"
+ help
+ Enable support for SPI DM flash drivers in TPL.
+
+config TPL_YMODEM_SUPPORT
+ bool "Support loading using Ymodem"
+ depends on TPL_SERIAL
+ help
+ While loading from serial is slow it can be a useful backup when
+ there is no other option. The Ymodem protocol provides a reliable
+ means of transmitting U-Boot over a serial line for using in TPL,
+ with a checksum to ensure correctness.
+
+endmenu
diff --git a/common/spl/Kconfig.vpl b/common/spl/Kconfig.vpl
new file mode 100644
index 0000000..ba1ea60
--- /dev/null
+++ b/common/spl/Kconfig.vpl
@@ -0,0 +1,201 @@
+menu "VPL options"
+ depends on VPL
+
+config VPL_BANNER_PRINT
+ bool "Enable output of the VPL banner 'U-Boot VPL ...'"
+ default y
+ help
+ If this option is enabled, VPL will print the banner with version
+ info. Disabling this option could be useful to reduce VPL boot time
+ (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
+
+config VPL_BOARD_INIT
+ bool "Call board-specific initialization in VPL"
+ help
+ If this option is enabled, U-Boot will call the function
+ spl_board_init() from board_init_r(). This function should be
+ provided by the board.
+
+config VPL_CACHE
+ depends on CACHE
+ bool "Support cache drivers in VPL"
+ help
+ Enable support for cache drivers in VPL.
+
+config VPL_CRC32
+ bool "Support CRC32 in VPL"
+ default y if VPL_ENV_SUPPORT || VPL_BLOBLIST
+ help
+ Enable this to support CRC32 in uImages or FIT images within VPL.
+ This is a 32-bit checksum value that can be used to verify images.
+ For FIT images, this is the least secure type of checksum, suitable
+ for detected accidental image corruption. For secure applications you
+ should consider SHA1 or SHA256.
+
+config VPL_DM_SPI
+ bool "Support SPI DM drivers in VPL"
+ help
+ Enable support for SPI DM drivers in VPL.
+
+config VPL_DM_SPI_FLASH
+ bool "Support SPI DM FLASH drivers in VPL"
+ help
+ Enable support for SPI DM flash drivers in VPL.
+
+config VPL_FRAMEWORK
+ bool "Support VPL based upon the common SPL framework"
+ default y
+ help
+ Enable the SPL framework under common/spl/ for VPL builds.
+ This framework supports MMC, NAND and YMODEM and other methods
+ loading of U-Boot's next stage. If unsure, say Y.
+
+config VPL_HANDOFF
+ bool "Pass hand-off information from VPL to SPL"
+ depends on HANDOFF && VPL_BLOBLIST
+ default y
+ help
+ This option enables VPL to write handoff information. This can be
+ used to pass information like the size of SDRAM from VPL to SPL. Also
+ VPL can receive information from TPL in the same place if that is
+ enabled.
+
+config VPL_LIBCOMMON_SUPPORT
+ bool "Support common libraries"
+ default y if SPL_LIBCOMMON_SUPPORT
+ help
+ Enable support for common U-Boot libraries within VPL. See
+ SPL_LIBCOMMON_SUPPORT for details.
+
+config VPL_LIBGENERIC_SUPPORT
+ bool "Support generic libraries"
+ default y if SPL_LIBGENERIC_SUPPORT
+ help
+ Enable support for generic U-Boot libraries within VPL. These
+ libraries include generic code to deal with device tree, hashing,
+ printf(), compression and the like. This option is enabled on many
+ boards. Enable this option to build the code in lib/ as part of a
+ VPL build.
+
+config VPL_DRIVERS_MISC
+ bool "Support misc drivers"
+ default y if TPL_DRIVERS_MISC
+ help
+ Enable miscellaneous drivers in VPL. These drivers perform various
+ tasks that don't fall nicely into other categories, Enable this
+ option to build the drivers in drivers/misc as part of a VPL
+ build, for those that support building in VPL (not all drivers do).
+
+config VPL_ENV_SUPPORT
+ bool "Support an environment"
+ help
+ Enable environment support in VPL. The U-Boot environment provides
+ a number of settings (essentially name/value pairs) which can
+ control many aspects of U-Boot's operation. Enabling this option will
+ make env_get() and env_set() available in VSPL.
+
+config VPL_GPIO
+ bool "Support GPIO in VPL"
+ default y if SPL_GPIO
+ help
+ Enable support for GPIOs (General-purpose Input/Output) in VPL.
+ GPIOs allow U-Boot to read the state of an input line (high or
+ low) and set the state of an output line. This can be used to
+ drive LEDs, control power to various system parts and read user
+ input. GPIOs can be useful in VPL to enable a 'sign-of-life' LED,
+ for example. Enable this option to build the drivers in
+ drivers/gpio as part of a VPL build.
+
+config VPL_HANDOFF
+ bool "Pass hand-off information from VPL to SPL and U-Boot proper"
+ depends on HANDOFF && VPL_BLOBLIST
+ default y
+ help
+ This option enables VPL to write handoff information. This can be
+ used to pass information like the size of SDRAM from VPL to U-Boot
+ proper. The information is also available to VPL if it is useful
+ there.
+
+config VPL_HASH
+ bool "Support hashing drivers in VPL"
+ select SHA1
+ select SHA256
+ help
+ Enable hashing drivers in VPL. These drivers can be used to
+ accelerate secure boot processing in secure applications. Enable
+ this option to build system-specific drivers for hash acceleration
+ as part of a VPL build.
+
+config VPL_I2C_SUPPORT
+ bool "Support I2C in VPL"
+ default y if SPL_I2C_SUPPORT
+ help
+ Enable support for the I2C bus in VPL. Vee SPL_I2C_SUPPORT for
+ details.
+
+config VPL_PCH_SUPPORT
+ bool "Support PCH drivers"
+ default y if TPL_PCH_SUPPORT
+ help
+ Enable support for PCH (Platform Controller Hub) devices in VPL.
+ These are used to set up GPIOs and the SPI peripheral early in
+ boot. This enables the drivers in drivers/pch as part of a VPL
+ build.
+
+config VPL_PCI
+ bool "Support PCI drivers"
+ default y if SPL_PCI
+ help
+ Enable support for PCI in VPL. For platforms that need PCI to boot,
+ or must perform some init using PCI in VPL, this provides the
+ necessary driver support. This enables the drivers in drivers/pci
+ as part of a VPL build.
+
+config VPL_RTC
+ bool "Support RTC drivers"
+ help
+ Enable RTC (Real-time Clock) support in VPL. This includes support
+ for reading and setting the time. Some RTC devices also have some
+ non-volatile (battery-backed) memory which is accessible if
+ needed. This enables the drivers in drivers/rtc as part of a VPL
+ build.
+
+config VPL_SERIAL
+ bool "Support serial"
+ default y if TPL_SERIAL
+ select VPL_PRINTF
+ select VPL_STRTO
+ help
+ Enable support for serial in VPL. See SPL_SERIAL_SUPPORT for
+ details.
+
+config VPL_SIZE_LIMIT
+ hex "Maximum size of VPL image"
+ default 0x0
+ help
+ Specifies the maximum length of the U-Boot VPL image.
+ If this value is zero, it is ignored.
+
+config VPL_SPI
+ bool "Support SPI drivers"
+ help
+ Enable support for using SPI in VPL. See SPL_SPI_SUPPORT for
+ details.
+
+config VPL_SPI_FLASH_SUPPORT
+ bool "Support SPI flash drivers"
+ help
+ Enable support for using SPI flash in VPL, and loading U-Boot from
+ SPI flash. SPI flash (Serial Peripheral Bus flash) is named after
+ the SPI bus that is used to connect it to a system. It is a simple
+ but fast bidirectional 4-wire bus (clock, chip select and two data
+ lines). This enables the drivers in drivers/mtd/spi as part of a
+ VPL build. This normally requires VPL_SPI_SUPPORT.
+
+config VPL_TEXT_BASE
+ hex "VPL Text Base"
+ default 0x0
+ help
+ The address in memory that VPL will be running from.
+
+endmenu
diff --git a/common/spl/spl.c b/common/spl/spl.c
index c8c463f..2a69a7c 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -19,6 +19,7 @@
#include <mapmem.h>
#include <serial.h>
#include <spl.h>
+#include <system-constants.h>
#include <asm/global_data.h>
#include <asm-generic/gpio.h>
#include <asm/u-boot.h>
@@ -728,9 +729,8 @@
spl_set_bd();
-#if defined(CONFIG_SYS_SPL_MALLOC_START)
- mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
- CONFIG_SYS_SPL_MALLOC_SIZE);
+#if defined(CONFIG_SYS_SPL_MALLOC)
+ mem_malloc_init(SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#endif
if (!(gd->flags & GD_FLG_SPL_INIT)) {
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 6116a68..f661474 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -229,7 +229,7 @@
{
int ret;
-#if defined(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
+#if CONFIG_VAL(SYS_MMCSD_RAW_MODE_ARGS_SECTOR)
unsigned long count;
count = blk_dread(mmc_get_blk_desc(mmc),
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 067a2d4..7986e93 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -74,8 +74,8 @@
(void *)(CONFIG_SYS_OS_BASE +
sizeof(struct image_header)),
spl_image->size);
-#ifdef CONFIG_SYS_FDT_BASE
- spl_image->arg = (void *)CONFIG_SYS_FDT_BASE;
+#ifdef CONFIG_SYS_SPL_ARGS_ADDR
+ spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
#endif
return 0;
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index 1f3a144..1351d78 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -21,10 +21,6 @@
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
#endif
-#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#endif
-
#ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR
/* Dummy value to make the compiler happy */
#define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100
@@ -73,21 +69,11 @@
int err = 0;
struct blk_desc *stor_dev;
-#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI)
- err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE);
-#endif
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: sata init failed: err - %d\n", err);
-#endif
- return err;
- } else {
- /* try to recognize storage devices immediately */
- scsi_scan(false);
- stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0);
- if (!stor_dev)
- return -ENODEV;
- }
+ /* try to recognize storage devices immediately */
+ scsi_scan(false);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0);
+ if (!stor_dev)
+ return -ENODEV;
#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot() ||
diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c
index 33863fe..e9a40b0 100644
--- a/common/spl/spl_xip.c
+++ b/common/spl/spl_xip.c
@@ -14,7 +14,7 @@
{
#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
- spl_image->arg = (void *)CONFIG_SYS_FDT_BASE;
+ spl_image->arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
spl_image->name = "Linux";
spl_image->os = IH_OS_LINUX;
spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index 72f8ce9..6c56cdc 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -15,6 +15,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index 0a69871..f266c0e 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -15,6 +15,8 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
@@ -37,6 +39,7 @@
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
+CONFIG_SYS_CFI_FLASH_STATUS_POLL=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 90f1230..026668b 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -11,7 +11,9 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 99f5785..7e9b92e 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -9,7 +9,9 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index f9d17b1..625a331 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -13,6 +13,8 @@
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
+CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 8c90435..5e0396c 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -15,7 +15,9 @@
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_DFU_RAM=y
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 918fc64..e0db1e6 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -13,7 +13,9 @@
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 903e3fd..a78cbfb 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -11,7 +11,9 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SCSI_AHCI=y
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index c060506..da3532c 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -9,7 +9,9 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index cf3fc68..0563a51 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -11,7 +11,9 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_STACK=0x8000
CONFIG_SPL_I2C=y
+CONFIG_SYS_PBSIZE=1024
CONFIG_SCSI_AHCI=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 81c2743..4993cf7 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -12,7 +12,9 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MAL