// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	interrupt-parent = <&intc>;

	qcom,msm-id = <292 0x0>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: memory@85800000 {
			reg = <0x0 0x85800000 0x0 0x600000>;
			no-map;
		};

		xbl_mem: memory@85e00000 {
			reg = <0x0 0x85e00000 0x0 0x100000>;
			no-map;
		};

		smem_mem: smem-mem@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
		};

		tz_mem: memory@86200000 {
			reg = <0x0 0x86200000 0x0 0x2d00000>;
			no-map;
		};

		rmtfs_mem: memory@88f00000 {
			compatible = "qcom,rmtfs-mem";
			reg = <0x0 0x88f00000 0x0 0x200000>;
			no-map;

			qcom,client-id = <1>;
			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
		};

		spss_mem: memory@8ab00000 {
			reg = <0x0 0x8ab00000 0x0 0x700000>;
			no-map;
		};

		adsp_mem: memory@8b200000 {
			reg = <0x0 0x8b200000 0x0 0x1a00000>;
			no-map;
		};

		mpss_mem: memory@8cc00000 {
			reg = <0x0 0x8cc00000 0x0 0x7000000>;
			no-map;
		};

		venus_mem: memory@93c00000 {
			reg = <0x0 0x93c00000 0x0 0x500000>;
			no-map;
		};

		mba_mem: memory@94100000 {
			reg = <0x0 0x94100000 0x0 0x200000>;
			no-map;
		};

		slpi_mem: memory@94300000 {
			reg = <0x0 0x94300000 0x0 0xf00000>;
			no-map;
		};

		ipa_fw_mem: memory@95200000 {
			reg = <0x0 0x95200000 0x0 0x10000>;
			no-map;
		};

		ipa_gsi_mem: memory@95210000 {
			reg = <0x0 0x95210000 0x0 0x5000>;
			no-map;
		};

		gpu_mem: memory@95600000 {
			reg = <0x0 0x95600000 0x0 0x100000>;
			no-map;
		};

		wlan_msa_mem: memory@95700000 {
			reg = <0x0 0x95700000 0x0 0x100000>;
			no-map;
		};

		mdata_mem: mpss-metadata {
			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
			size = <0x0 0x4000>;
			no-map;
		};
	};

	clocks {
		xo: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x2>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
			next-level-cache = <&L2_0>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x3>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
			next-level-cache = <&L2_0>;
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1536>;
			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <1536>;
			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
			next-level-cache = <&L2_1>;
		};

		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x102>;
			enable-method = "psci";
			capacity-dmips-mhz = <1536>;
			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
			next-level-cache = <&L2_1>;
		};

		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "qcom,kryo280";
			reg = <0x0 0x103>;
			enable-method = "psci";
			capacity-dmips-mhz = <1536>;
			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
			next-level-cache = <&L2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
				compatible = "arm,idle-state";
				idle-state-name = "little-retention";
				/* CPU Retention (C2D), L2 Active */
				arm,psci-suspend-param = <0x00000002>;
				entry-latency-us = <81>;
				exit-latency-us = <86>;
				min-residency-us = <504>;
			};

			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
				compatible = "arm,idle-state";
				idle-state-name = "little-power-collapse";
				/* CPU + L2 Power Collapse (C3, D4) */
				arm,psci-suspend-param = <0x40000003>;
				entry-latency-us = <814>;
				exit-latency-us = <4562>;
				min-residency-us = <9183>;
				local-timer-stop;
			};

			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
				compatible = "arm,idle-state";
				idle-state-name = "big-retention";
				/* CPU Retention (C2D), L2 Active */
				arm,psci-suspend-param = <0x00000002>;
				entry-latency-us = <79>;
				exit-latency-us = <82>;
				min-residency-us = <1302>;
			};

			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
				compatible = "arm,idle-state";
				idle-state-name = "big-power-collapse";
				/* CPU + L2 Power Collapse (C3, D4) */
				arm,psci-suspend-param = <0x40000003>;
				entry-latency-us = <724>;
				exit-latency-us = <2027>;
				min-residency-us = <9419>;
				local-timer-stop;
			};
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8998", "qcom,scm";
		};
	};

	dsi_opp_table: opp-table-dsi {
		compatible = "operating-points-v2";

		opp-131250000 {
			opp-hz = /bits/ 64 <131250000>;
			required-opps = <&rpmpd_opp_low_svs>;
		};

		opp-210000000 {
			opp-hz = /bits/ 64 <210000000>;
			required-opps = <&rpmpd_opp_svs>;
		};

		opp-312500000 {
			opp-hz = /bits/ 64 <312500000>;
			required-opps = <&rpmpd_opp_nom>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	rpm: remoteproc {
		compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";

		glink-edge {
			compatible = "qcom,glink-rpm";

			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,rpm-msg-ram = <&rpm_msg_ram>;
			mboxes = <&apcs_glb 0>;

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8998";
				qcom,glink-channels = "rpm_requests";

				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
					clocks = <&xo>;
					clock-names = "xo";
					#clock-cells = <1>;
				};

				rpmpd: power-controller {
					compatible = "qcom,msm8998-rpmpd";
					#power-domain-cells = <1>;
					operating-points-v2 = <&rpmpd_opp_table>;

					rpmpd_opp_table: opp-table {
						compatible = "operating-points-v2";

						rpmpd_opp_ret: opp1 {
							opp-level = <RPM_SMD_LEVEL_RETENTION>;
						};

						rpmpd_opp_ret_plus: opp2 {
							opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
						};

						rpmpd_opp_min_svs: opp3 {
							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
						};

						rpmpd_opp_low_svs: opp4 {
							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
						};

						rpmpd_opp_svs: opp5 {
							opp-level = <RPM_SMD_LEVEL_SVS>;
						};

						rpmpd_opp_svs_plus: opp6 {
							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
						};

						rpmpd_opp_nom: opp7 {
							opp-level = <RPM_SMD_LEVEL_NOM>;
						};

						rpmpd_opp_nom_plus: opp8 {
							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
						};

						rpmpd_opp_turbo: opp9 {
							opp-level = <RPM_SMD_LEVEL_TURBO>;
						};

						rpmpd_opp_turbo_plus: opp10 {
							opp-level = <RPM_SMD_LEVEL_BINNING>;
						};
					};
				};
			};
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-lpass {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs_glb 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-mpss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 26>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;

		slpi_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		slpi_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	thermal-zones {
		cpu0-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 1>;

			trips {
				cpu0_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu0_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 2>;

			trips {
				cpu1_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu1_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 3>;

			trips {
				cpu2_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu2_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 4>;

			trips {
				cpu3_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu3_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu4-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 7>;

			trips {
				cpu4_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu4_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu5-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 8>;

			trips {
				cpu5_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu5_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu6-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 9>;

			trips {
				cpu6_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu6_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu7-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 10>;

			trips {
				cpu7_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		gpu-bottom-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 12>;

			trips {
				gpu1_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		gpu-top-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 13>;

			trips {
				gpu2_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		clust0-mhm-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 5>;

			trips {
				cluster0_mhm_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		clust1-mhm-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 6>;

			trips {
				cluster1_mhm_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		cluster1-l2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 11>;

			trips {
				cluster1_l2_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		modem-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 1>;

			trips {
				modem_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		mem-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 2>;

			trips {
				mem_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		wlan-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 3>;

			trips {
				wlan_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		q6-dsp-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 4>;

			trips {
				q6_dsp_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		camera-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 5>;

			trips {
				camera_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		multimedia-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 6>;

			trips {
				multimedia_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};

	soc: soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-msm8998";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x00100000 0xb0000>;

			clock-names = "xo", "sleep_clk";
			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;

			/*
			 * The hypervisor typically configures the memory region where these clocks
			 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
			 * these clocks on a device with such configuration (e.g. because they are
			 * enabled but unused during boot-up), the device will most likely decide
			 * to reboot.
			 * In light of that, we are conservative here and we list all such clocks
			 * as protected. The board dts (or a user-supplied dts) can override the
			 * list of protected clocks if it differs from the norm, and it is in fact
			 * desired for the HLOS to manage these clocks
			 */
			protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
					   <SSC_XO>,
					   <SSC_CNOC_AHBS_CLK>;
		};

		rpm_msg_ram: sram@778000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x00778000 0x7000>;
		};

		qfprom: qfprom@784000 {
			compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
			reg = <0x00784000 0x621c>;
			#address-cells = <1>;
			#size-cells = <1>;

			qusb2_hstx_trim: hstx-trim@23a {
				reg = <0x23a 0x1>;
				bits = <0 4>;
			};
		};

		tsens0: thermal@10ab000 {
			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
			reg = <0x010ab000 0x1000>, /* TM */
			      <0x010aa000 0x1000>; /* SROT */
			#qcom,sensors = <14>;
			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		tsens1: thermal@10ae000 {
			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
			reg = <0x010ae000 0x1000>, /* TM */
			      <0x010ad000 0x1000>; /* SROT */
			#qcom,sensors = <8>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		anoc1_smmu: iommu@1680000 {
			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
			reg = <0x01680000 0x10000>;
			#iommu-cells = <1>;

			#global-interrupts = <0>;
			interrupts =
				<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
		};

		anoc2_smmu: iommu@16c0000 {
			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
			reg = <0x016c0000 0x40000>;
			#iommu-cells = <1>;

			#global-interrupts = <0>;
			interrupts =
				<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
		};

		pcie0: pci@1c00000 {
			compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
			reg = <0x01c00000 0x2000>,
			      <0x1b000000 0xf1d>,
			      <0x1b000f20 0xa8>,
			      <0x1b100000 0x100000>;
			reg-names = "parf", "dbi", "elbi", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			#address-cells = <3>;
			#size-cells = <2>;
			num-lanes = <1>;
			phys = <&pcie_phy>;
			phy-names = "pciephy";
			status = "disabled";

			ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;

			#interrupt-cells = <1>;
			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
				 <&gcc GCC_PCIE_0_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
			clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";

			power-domains = <&gcc PCIE_0_GDSC>;
			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
		};

		pcie_phy: phy@1c06000 {
			compatible = "qcom,msm8998-qmp-pcie-phy";
			reg = <0x01c06000 0x1000>;
			status = "disabled";

			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_CLKREF_CLK>,
				 <&gcc GCC_PCIE_0_PIPE_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "pipe";

			clock-output-names = "pcie_0_pipe_clk_src";
			#clock-cells = <0>;

			#phy-cells = <0>;

			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
			reset-names = "phy", "common";

			vdda-phy-supply = <&vreg_l1a_0p875>;
			vdda-pll-supply = <&vreg_l2a_1p2>;
		};

		ufshc: ufshc@1da4000 {
			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
			reg = <0x01da4000 0x2500>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufsphy_lanes>;
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			power-domains = <&gcc UFS_GDSC>;
			status = "disabled";
			#reset-cells = <1>;

			clock-names =
				"core_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk",
				"rx_lane1_sync_clk";
			clocks =
				<&gcc GCC_UFS_AXI_CLK>,
				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
				<&gcc GCC_UFS_AHB_CLK>,
				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
				<&rpmcc RPM_SMD_LN_BB_CLK1>,
				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
			freq-table-hz =
				<50000000 200000000>,
				<0 0>,
				<0 0>,
				<37500000 150000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>;

			resets = <&gcc GCC_UFS_BCR>;
			reset-names = "rst";
		};

		ufsphy: phy@1da7000 {
			compatible = "qcom,msm8998-qmp-ufs-phy";
			reg = <0x01da7000 0x18c>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
			ranges;

			clock-names =
				"ref",
				"ref_aux";
			clocks =
				<&gcc GCC_UFS_CLKREF_CLK>,
				<&gcc GCC_UFS_PHY_AUX_CLK>;

			reset-names = "ufsphy";
			resets = <&ufshc 0>;

			ufsphy_lanes: phy@1da7400 {
				reg = <0x01da7400 0x128>,
				      <0x01da7600 0x1fc>,
				      <0x01da7c00 0x1dc>,
				      <0x01da7800 0x128>,
				      <0x01da7a00 0x1fc>;
				#phy-cells = <0>;
			};
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x01f40000 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr_regs_1: syscon@1f60000 {
			compatible = "qcom,msm8998-tcsr", "syscon";
			reg = <0x01f60000 0x20000>;
		};

		tlmm: pinctrl@3400000 {
			compatible = "qcom,msm8998-pinctrl";
			reg = <0x03400000 0xc00000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&tlmm 0 0 150>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;

			sdc2_on: sdc2-on-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <16>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <10>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <10>;
					bias-pull-up;
				};
			};

			sdc2_off: sdc2-off-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <2>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <2>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			sdc2_cd: sdc2-cd-state {
				pins = "gpio95";
				function = "gpio";
				bias-pull-up;
				drive-strength = <2>;
			};

			blsp1_uart3_on: blsp1-uart3-on-state {
				tx-pins {
					pins = "gpio45";
					function = "blsp_uart3_a";
					drive-strength = <2>;
					bias-disable;
				};

				rx-pins {
					pins = "gpio46";
					function = "blsp_uart3_a";
					drive-strength = <2>;
					bias-disable;
				};

				cts-pins {
					pins = "gpio47";
					function = "blsp_uart3_a";
					drive-strength = <2>;
					bias-disable;
				};

				rfr-pins {
					pins = "gpio48";
					function = "blsp_uart3_a";
					drive-strength = <2>;
					bias-disable;
				};
			};

			blsp1_i2c1_default: blsp1-i2c1-default-state {
				pins = "gpio2", "gpio3";
				function = "blsp_i2c1";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
				pins = "gpio2", "gpio3";
				function = "blsp_i2c1";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp1_i2c2_default: blsp1-i2c2-default-state {
				pins = "gpio32", "gpio33";
				function = "blsp_i2c2";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
				pins = "gpio32", "gpio33";
				function = "blsp_i2c2";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp1_i2c3_default: blsp1-i2c3-default-state {
				pins = "gpio47", "gpio48";
				function = "blsp_i2c3";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
				pins = "gpio47", "gpio48";
				function = "blsp_i2c3";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp1_i2c4_default: blsp1-i2c4-default-state {
				pins = "gpio10", "gpio11";
				function = "blsp_i2c4";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
				pins = "gpio10", "gpio11";
				function = "blsp_i2c4";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp1_i2c5_default: blsp1-i2c5-default-state {
				pins = "gpio87", "gpio88";
				function = "blsp_i2c5";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
				pins = "gpio87", "gpio88";
				function = "blsp_i2c5";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp1_i2c6_default: blsp1-i2c6-default-state {
				pins = "gpio43", "gpio44";
				function = "blsp_i2c6";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
				pins = "gpio43", "gpio44";
				function = "blsp_i2c6";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp1_spi_b_default: blsp1-spi-b-default-state {
				pins = "gpio23", "gpio28";
				function = "blsp1_spi_b";
				drive-strength = <6>;
				bias-disable;
			};

			blsp1_spi1_default: blsp1-spi1-default-state {
				pins = "gpio0", "gpio1", "gpio2", "gpio3";
				function = "blsp_spi1";
				drive-strength = <6>;
				bias-disable;
			};

			blsp1_spi2_default: blsp1-spi2-default-state {
				pins = "gpio31", "gpio34", "gpio32", "gpio33";
				function = "blsp_spi2";
				drive-strength = <6>;
				bias-disable;
			};

			blsp1_spi3_default: blsp1-spi3-default-state {
				pins = "gpio45", "gpio46", "gpio47", "gpio48";
				function = "blsp_spi2";
				drive-strength = <6>;
				bias-disable;
			};

			blsp1_spi4_default: blsp1-spi4-default-state {
				pins = "gpio8", "gpio9", "gpio10", "gpio11";
				function = "blsp_spi4";
				drive-strength = <6>;
				bias-disable;
			};

			blsp1_spi5_default: blsp1-spi5-default-state {
				pins = "gpio85", "gpio86", "gpio87", "gpio88";
				function = "blsp_spi5";
				drive-strength = <6>;
				bias-disable;
			};

			blsp1_spi6_default: blsp1-spi6-default-state {
				pins = "gpio41", "gpio42", "gpio43", "gpio44";
				function = "blsp_spi6";
				drive-strength = <6>;
				bias-disable;
			};


			/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
			blsp2_i2c1_default: blsp2-i2c1-default-state {
				pins = "gpio55", "gpio56";
				function = "blsp_i2c7";
				drive-strength = <2>;
				bias-disable;
			};

			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
				pins = "gpio55", "gpio56";
				function = "blsp_i2c7";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp2_i2c2_default: blsp2-i2c2-default-state {
				pins = "gpio6", "gpio7";
				function = "blsp_i2c8";
				drive-strength = <2>;
				bias-disable;
			};

			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
				pins = "gpio6", "gpio7";
				function = "blsp_i2c8";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp2_i2c3_default: blsp2-i2c3-default-state {
				pins = "gpio51", "gpio52";
				function = "blsp_i2c9";
				drive-strength = <2>;
				bias-disable;
			};

			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
				pins = "gpio51", "gpio52";
				function = "blsp_i2c9";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp2_i2c4_default: blsp2-i2c4-default-state {
				pins = "gpio67", "gpio68";
				function = "blsp_i2c10";
				drive-strength = <2>;
				bias-disable;
			};

			blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
				pins = "gpio67", "gpio68";
				function = "blsp_i2c10";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp2_i2c5_default: blsp2-i2c5-default-state {
				pins = "gpio60", "gpio61";
				function = "blsp_i2c11";
				drive-strength = <2>;
				bias-disable;
			};

			blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
				pins = "gpio60", "gpio61";
				function = "blsp_i2c11";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp2_i2c6_default: blsp2-i2c6-default-state {
				pins = "gpio83", "gpio84";
				function = "blsp_i2c12";
				drive-strength = <2>;
				bias-disable;
			};

			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
				pins = "gpio83", "gpio84";
				function = "blsp_i2c12";
				drive-strength = <2>;
				bias-pull-up;
			};

			blsp2_spi1_default: blsp2-spi1-default-state {
				pins = "gpio53", "gpio54", "gpio55", "gpio56";
				function = "blsp_spi7";
				drive-strength = <6>;
				bias-disable;
			};

			blsp2_spi2_default: blsp2-spi2-default-state {
				pins = "gpio4", "gpio5", "gpio6", "gpio7";
				function = "blsp_spi8";
				drive-strength = <6>;
				bias-disable;
			};

			blsp2_spi3_default: blsp2-spi3-default-state {
				pins = "gpio49", "gpio50", "gpio51", "gpio52";
				function = "blsp_spi9";
				drive-strength = <6>;
				bias-disable;
			};

			blsp2_spi4_default: blsp2-spi4-default-state {
				pins = "gpio65", "gpio66", "gpio67", "gpio68";
				function = "blsp_spi10";
				drive-strength = <6>;
				bias-disable;
			};

			blsp2_spi5_default: blsp2-spi5-default-state {
				pins = "gpio58", "gpio59", "gpio60", "gpio61";
				function = "blsp_spi11";
				drive-strength = <6>;
				bias-disable;
			};

			blsp2_spi6_default: blsp2-spi6-default-state {
				pins = "gpio81", "gpio82", "gpio83", "gpio84";
				function = "blsp_spi12";
				drive-strength = <6>;
				bias-disable;
			};
		};

		remoteproc_mss: remoteproc@4080000 {
			compatible = "qcom,msm8998-mss-pil";
			reg = <0x04080000 0x100>, <0x04180000 0x20>;
			reg-names = "qdsp6", "rmb";

			interrupts-extended =
				<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack",
					  "shutdown-ack";

			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
				 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
				 <&rpmcc RPM_SMD_QDSS_CLK>,
				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
			clock-names = "iface", "bus", "mem", "gpll0_mss",
				      "snoc_axi", "mnoc_axi", "qdss", "xo";

			qcom,smem-states = <&modem_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			resets = <&gcc GCC_MSS_RESTART>;
			reset-names = "mss_restart";

			qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;

			power-domains = <&rpmpd MSM8998_VDDCX>,
					<&rpmpd MSM8998_VDDMX>;
			power-domain-names = "cx", "mx";

			status = "disabled";

			mba {
				memory-region = <&mba_mem>;
			};

			mpss {
				memory-region = <&mpss_mem>;
			};

			metadata {
				memory-region = <&mdata_mem>;
			};

			glink-edge {
				interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
				label = "modem";
				qcom,remote-pid = <1>;
				mboxes = <&apcs_glb 15>;
			};
		};

		adreno_gpu: gpu@5000000 {
			compatible = "qcom,adreno-540.1", "qcom,adreno";
			reg = <0x05000000 0x40000>;
			reg-names = "kgsl_3d0_reg_memory";

			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
				<&gpucc RBBMTIMER_CLK>,
				<&gcc GCC_BIMC_GFX_CLK>,
				<&gcc GCC_GPU_BIMC_GFX_CLK>,
				<&gpucc RBCPR_CLK>,
				<&gpucc GFX3D_CLK>;
			clock-names = "iface",
				"rbbmtimer",
				"mem",
				"mem_iface",
				"rbcpr",
				"core";

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
			iommus = <&adreno_smmu 0>;
			operating-points-v2 = <&gpu_opp_table>;
			power-domains = <&rpmpd MSM8998_VDDMX>;
			status = "disabled";

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";
				opp-710000097 {
					opp-hz = /bits/ 64 <710000097>;
					opp-level = <RPM_SMD_LEVEL_TURBO>;
					opp-supported-hw = <0xff>;
				};

				opp-670000048 {
					opp-hz = /bits/ 64 <670000048>;
					opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
					opp-supported-hw = <0xff>;
				};

				opp-596000097 {
					opp-hz = /bits/ 64 <596000097>;
					opp-level = <RPM_SMD_LEVEL_NOM>;
					opp-supported-hw = <0xff>;
				};

				opp-515000097 {
					opp-hz = /bits/ 64 <515000097>;
					opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
					opp-supported-hw = <0xff>;
				};

				opp-414000000 {
					opp-hz = /bits/ 64 <414000000>;
					opp-level = <RPM_SMD_LEVEL_SVS>;
					opp-supported-hw = <0xff>;
				};

				opp-342000000 {
					opp-hz = /bits/ 64 <342000000>;
					opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
					opp-supported-hw = <0xff>;
				};

				opp-257000000 {
					opp-hz = /bits/ 64 <257000000>;
					opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
					opp-supported-hw = <0xff>;
				};
			};
		};

		adreno_smmu: iommu@5040000 {
			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
			reg = <0x05040000 0x10000>;
			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
				 <&gcc GCC_BIMC_GFX_CLK>,
				 <&gcc GCC_GPU_BIMC_GFX_CLK>;
			clock-names = "iface", "mem", "mem_iface";

			#global-interrupts = <0>;
			#iommu-cells = <1>;
			interrupts =
				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
			/*
			 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
			 * GPU-CX for SMMU but we need both of them up for Adreno.
			 * Contemporarily, we also need to manage the VDDMX rpmpd
			 * domain in the Adreno driver.
			 * Enable GPU CX/GX GDSCs here so that we can manage the
			 * SoC VDDMX RPM Power Domain in the Adreno driver.
			 */
			power-domains = <&gpucc GPU_GX_GDSC>;
			status = "disabled";
		};

		gpucc: clock-controller@5065000 {
			compatible = "qcom,msm8998-gpucc";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x05065000 0x9000>;

			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
				 <&gcc GCC_GPU_GPLL0_CLK>;
			clock-names = "xo",
				      "gpll0";
		};

		remoteproc_slpi: remoteproc@5800000 {
			compatible = "qcom,msm8998-slpi-pas";
			reg = <0x05800000 0x4040>;

			interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			px-supply = <&vreg_lvs2a_1p8>;

			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
				 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
			clock-names = "xo", "aggre2";

			memory-region = <&slpi_mem>;

			qcom,smem-states = <&slpi_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			power-domains = <&rpmpd MSM8998_SSCCX>;
			power-domain-names = "ssc_cx";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
				label = "dsps";
				qcom,remote-pid = <3>;
				mboxes = <&apcs_glb 27>;
			};
		};

		stm: stm@6002000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x06002000 0x1000>,
			      <0x16280000 0x180000>;
			reg-names = "stm-base", "stm-stimulus-base";
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					stm_out: endpoint {
						remote-endpoint = <&funnel0_in7>;
					};
				};
			};
		};

		funnel1: funnel@6041000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x06041000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					funnel0_out: endpoint {
						remote-endpoint =
						  <&merge_funnel_in0>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@7 {
					reg = <7>;
					funnel0_in7: endpoint {
						remote-endpoint = <&stm_out>;
					};
				};
			};
		};

		funnel2: funnel@6042000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x06042000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint =
						  <&merge_funnel_in1>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@6 {
					reg = <6>;
					funnel1_in6: endpoint {
						remote-endpoint =
						  <&apss_merge_funnel_out>;
					};
				};
			};
		};

		funnel3: funnel@6045000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x06045000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					merge_funnel_out: endpoint {
						remote-endpoint =
						  <&etf_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					merge_funnel_in0: endpoint {
						remote-endpoint =
						  <&funnel0_out>;
					};
				};

				port@1 {
					reg = <1>;
					merge_funnel_in1: endpoint {
						remote-endpoint =
						  <&funnel1_out>;
					};
				};
			};
		};

		replicator1: replicator@6046000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x06046000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					replicator_out: endpoint {
						remote-endpoint = <&etr_in>;
					};
				};
			};

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint = <&etf_out>;
					};
				};
			};
		};

		etf: etf@6047000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x06047000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					etf_out: endpoint {
						remote-endpoint =
						  <&replicator_in>;
					};
				};
			};

			in-ports {
				port {
					etf_in: endpoint {
						remote-endpoint =
						  <&merge_funnel_out>;
					};
				};
			};
		};

		etr: etr@6048000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x06048000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,scatter-gather;

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint =
						  <&replicator_out>;
					};
				};
			};
		};

		etm1: etm@7840000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07840000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU0>;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint =
						  <&apss_funnel_in0>;
					};
				};
			};
		};

		etm2: etm@7940000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07940000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU1>;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint =
						  <&apss_funnel_in1>;
					};
				};
			};
		};

		etm3: etm@7a40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07a40000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU2>;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint =
						  <&apss_funnel_in2>;
					};
				};
			};
		};

		etm4: etm@7b40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07b40000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU3>;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint =
						  <&apss_funnel_in3>;
					};
				};
			};
		};

		funnel4: funnel@7b60000 { /* APSS Funnel */
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07b60000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					apss_funnel_out: endpoint {
						remote-endpoint =
						  <&apss_merge_funnel_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					apss_funnel_in0: endpoint {
						remote-endpoint =
						  <&etm0_out>;
					};
				};

				port@1 {
					reg = <1>;
					apss_funnel_in1: endpoint {
						remote-endpoint =
						  <&etm1_out>;
					};
				};

				port@2 {
					reg = <2>;
					apss_funnel_in2: endpoint {
						remote-endpoint =
						  <&etm2_out>;
					};
				};

				port@3 {
					reg = <3>;
					apss_funnel_in3: endpoint {
						remote-endpoint =
						  <&etm3_out>;
					};
				};

				port@4 {
					reg = <4>;
					apss_funnel_in4: endpoint {
						remote-endpoint =
						  <&etm4_out>;
					};
				};

				port@5 {
					reg = <5>;
					apss_funnel_in5: endpoint {
						remote-endpoint =
						  <&etm5_out>;
					};
				};

				port@6 {
					reg = <6>;
					apss_funnel_in6: endpoint {
						remote-endpoint =
						  <&etm6_out>;
					};
				};

				port@7 {
					reg = <7>;
					apss_funnel_in7: endpoint {
						remote-endpoint =
						  <&etm7_out>;
					};
				};
			};
		};

		funnel5: funnel@7b70000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x07b70000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					apss_merge_funnel_out: endpoint {
						remote-endpoint =
						  <&funnel1_in6>;
					};
				};
			};

			in-ports {
				port {
					apss_merge_funnel_in: endpoint {
						remote-endpoint =
						  <&apss_funnel_out>;
					};
				};
			};
		};

		etm5: etm@7c40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07c40000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU4>;

			port {
				etm4_out: endpoint {
					remote-endpoint = <&apss_funnel_in4>;
				};
			};
		};

		etm6: etm@7d40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07d40000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU5>;

			port {
				etm5_out: endpoint {
					remote-endpoint = <&apss_funnel_in5>;
				};
			};
		};

		etm7: etm@7e40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07e40000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU6>;

			port {
				etm6_out: endpoint {
					remote-endpoint = <&apss_funnel_in6>;
				};
			};
		};

		etm8: etm@7f40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x07f40000 0x1000>;
			status = "disabled";

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU7>;

			port {
				etm7_out: endpoint {
					remote-endpoint = <&apss_funnel_in7>;
				};
			};
		};

		sram@290000 {
			compatible = "qcom,rpm-stats";
			reg = <0x00290000 0x10000>;
		};

		spmi_bus: spmi@800f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0800f000 0x1000>,
			      <0x08400000 0x1000000>,
			      <0x09400000 0x1000000>,
			      <0x0a400000 0x220000>,
			      <0x0800a000 0x3000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		usb3: usb@a8f8800 {
			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
			reg = <0x0a8f8800 0x400>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
				 <&gcc GCC_USB30_MASTER_CLK>,
				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
				 <&gcc GCC_USB30_SLEEP_CLK>,
				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi";

			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <120000000>;

			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "ss_phy_irq";

			power-domains = <&gcc USB_30_GDSC>;

			resets = <&gcc GCC_USB_30_BCR>;

			usb3_dwc3: usb@a800000 {
				compatible = "snps,dwc3";
				reg = <0x0a800000 0xcd00>;
				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&qusb2phy>, <&usb1_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
				snps,has-lpm-erratum;
				snps,hird-threshold = /bits/ 8 <0x10>;
			};
		};

		usb3phy: phy@c010000 {
			compatible = "qcom,msm8998-qmp-usb3-phy";
			reg = <0x0c010000 0x18c>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_USB3_CLKREF_CLK>;
			clock-names = "aux", "cfg_ahb", "ref";

			resets = <&gcc GCC_USB3_PHY_BCR>,
				 <&gcc GCC_USB3PHY_PHY_BCR>;
			reset-names = "phy", "common";

			usb1_ssphy: phy@c010200 {
				reg = <0xc010200 0x128>,
				      <0xc010400 0x200>,
				      <0xc010c00 0x20c>,
				      <0xc010600 0x128>,
				      <0xc010800 0x200>;
				#phy-cells = <0>;
				#clock-cells = <0>;
				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_phy_pipe_clk_src";
			};
		};

		qusb2phy: phy@c012000 {
			compatible = "qcom,msm8998-qusb2-phy";
			reg = <0x0c012000 0x2a8>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

			nvmem-cells = <&qusb2_hstx_trim>;
		};

		sdhc2: mmc@c0a4900 {
			compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
			reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
			reg-names = "hc", "core";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clock-names = "iface", "core", "xo";
			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
			bus-width = <4>;
			status = "disabled";
		};

		blsp1_dma: dma-controller@c144000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x0c144000 0x25000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			num-channels = <18>;
			qcom,num-ees = <4>;
		};

		blsp1_uart3: serial@c171000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x0c171000 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_uart3_on>;
			status = "disabled";
		};

		blsp1_i2c1: i2c@c175000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c175000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c1_default>;
			pinctrl-1 = <&blsp1_i2c1_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c2: i2c@c176000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c176000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c2_default>;
			pinctrl-1 = <&blsp1_i2c2_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c3: i2c@c177000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c177000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c3_default>;
			pinctrl-1 = <&blsp1_i2c3_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c4: i2c@c178000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c178000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c4_default>;
			pinctrl-1 = <&blsp1_i2c4_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c5: i2c@c179000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c179000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c5_default>;
			pinctrl-1 = <&blsp1_i2c5_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c6: i2c@c17a000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c17a000 0x600>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c6_default>;
			pinctrl-1 = <&blsp1_i2c6_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_spi1: spi@c175000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c175000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi1_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_spi2: spi@c176000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c176000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi2_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_spi3: spi@c177000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c177000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi3_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_spi4: spi@c178000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c178000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi4_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_spi5: spi@c179000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c179000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi5_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_spi6: spi@c17a000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c17a000 0x600>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi6_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_dma: dma-controller@c184000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x0c184000 0x25000>;
			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			num-channels = <18>;
			qcom,num-ees = <4>;
		};

		blsp2_uart1: serial@c1b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x0c1b0000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp2_i2c1: i2c@c1b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b5000 0x600>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c1_default>;
			pinctrl-1 = <&blsp2_i2c1_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c2: i2c@c1b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b6000 0x600>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c2_default>;
			pinctrl-1 = <&blsp2_i2c2_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c3: i2c@c1b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b7000 0x600>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c3_default>;
			pinctrl-1 = <&blsp2_i2c3_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c4: i2c@c1b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b8000 0x600>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c4_default>;
			pinctrl-1 = <&blsp2_i2c4_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c5: i2c@c1b9000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1b9000 0x600>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c5_default>;
			pinctrl-1 = <&blsp2_i2c5_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_i2c6: i2c@c1ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x0c1ba000 0x600>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c6_default>;
			pinctrl-1 = <&blsp2_i2c6_sleep>;
			clock-frequency = <400000>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_spi1: spi@c1b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c1b5000 0x600>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_spi1_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_spi2: spi@c1b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c1b6000 0x600>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_spi2_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_spi3: spi@c1b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c1b7000 0x600>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_spi3_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_spi4: spi@c1b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c1b8000 0x600>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_spi4_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_spi5: spi@c1b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c1b9000 0x600>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_spi5_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp2_spi6: spi@c1ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x0c1ba000 0x600>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_spi6_default>;

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmcc: clock-controller@c8c0000 {
			compatible = "qcom,mmcc-msm8998";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xc8c0000 0x40000>;

			clock-names = "xo",
				      "gpll0",
				      "dsi0dsi",
				      "dsi0byte",
				      "dsi1dsi",
				      "dsi1byte",
				      "hdmipll",
				      "dplink",
				      "dpvco",
				      "gpll0_div";
			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
				 <&gcc GCC_MMSS_GPLL0_CLK>,
				 <&mdss_dsi0_phy 1>,
				 <&mdss_dsi0_phy 0>,
				 <&mdss_dsi1_phy 1>,
				 <&mdss_dsi1_phy 0>,
				 <0>,
				 <0>,
				 <0>,
				 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
		};

		mdss: display-subsystem@c900000 {
			compatible = "qcom,msm8998-mdss";
			reg = <0x0c900000 0x1000>;
			reg-names = "mdss";

			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <1>;

			clocks = <&mmcc MDSS_AHB_CLK>,
				 <&mmcc MDSS_AXI_CLK>,
				 <&mmcc MDSS_MDP_CLK>;
			clock-names = "iface",
				      "bus",
				      "core";

			power-domains = <&mmcc MDSS_GDSC>;
			iommus = <&mmss_smmu 0>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			status = "disabled";

			mdss_mdp: display-controller@c901000 {
				compatible = "qcom,msm8998-dpu";
				reg = <0x0c901000 0x8f000>,
				      <0x0c9a8e00 0xf0>,
				      <0x0c9b0000 0x2008>,
				      <0x0c9b8000 0x1040>;
				reg-names = "mdp",
					    "regdma",
					    "vbif",
					    "vbif_nrt";

				interrupt-parent = <&mdss>;
				interrupts = <0>;

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MNOC_AHB_CLK>,
					 <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_VSYNC_CLK>;
				clock-names = "iface",
					      "bus",
					      "mnoc",
					      "core",
					      "vsync";

				assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
				assigned-clock-rates = <19200000>;

				operating-points-v2 = <&mdp_opp_table>;
				power-domains = <&rpmpd MSM8998_VDDMX>;

				mdp_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-171430000 {
						opp-hz = /bits/ 64 <171430000>;
						required-opps = <&rpmpd_opp_low_svs>;
					};

					opp-275000000 {
						opp-hz = /bits/ 64 <275000000>;
						required-opps = <&rpmpd_opp_svs>;
					};

					opp-330000000 {
						opp-hz = /bits/ 64 <330000000>;
						required-opps = <&rpmpd_opp_nom>;
					};

					opp-412500000 {
						opp-hz = /bits/ 64 <412500000>;
						required-opps = <&rpmpd_opp_turbo>;
					};
				};

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						dpu_intf1_out: endpoint {
							remote-endpoint = <&mdss_dsi0_in>;
						};
					};

					port@1 {
						reg = <1>;

						dpu_intf2_out: endpoint {
							remote-endpoint = <&mdss_dsi1_in>;
						};
					};
				};
			};

			mdss_dsi0: dsi@c994000 {
				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
				reg = <0x0c994000 0x400>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4>;

				clocks = <&mmcc MDSS_BYTE0_CLK>,
					 <&mmcc MDSS_BYTE0_INTF_CLK>,
					 <&mmcc MDSS_PCLK0_CLK>,
					 <&mmcc MDSS_ESC0_CLK>,
					 <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>;
				clock-names = "byte",
					      "byte_intf",
					      "pixel",
					      "core",
					      "iface",
					      "bus";
				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
						  <&mmcc PCLK0_CLK_SRC>;
				assigned-clock-parents = <&mdss_dsi0_phy 0>,
							 <&mdss_dsi0_phy 1>;

				operating-points-v2 = <&dsi_opp_table>;
				power-domains = <&rpmpd MSM8998_VDDCX>;

				phys = <&mdss_dsi0_phy>;
				phy-names = "dsi";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dsi0_in: endpoint {
							remote-endpoint = <&dpu_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dsi0_out: endpoint {
						};
					};
				};
			};

			mdss_dsi0_phy: phy@c994400 {
				compatible = "qcom,dsi-phy-10nm-8998";
				reg = <0x0c994400 0x200>,
				      <0x0c994600 0x280>,
				      <0x0c994a00 0x1e0>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
				clock-names = "iface", "ref";

				#clock-cells = <1>;
				#phy-cells = <0>;

				status = "disabled";
			};

			mdss_dsi1: dsi@c996000 {
				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
				reg = <0x0c996000 0x400>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <5>;

				clocks = <&mmcc MDSS_BYTE1_CLK>,
					 <&mmcc MDSS_BYTE1_INTF_CLK>,
					 <&mmcc MDSS_PCLK1_CLK>,
					 <&mmcc MDSS_ESC1_CLK>,
					 <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>;
				clock-names = "byte",
					      "byte_intf",
					      "pixel",
					      "core",
					      "iface",
					      "bus";
				assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
						  <&mmcc PCLK1_CLK_SRC>;
				assigned-clock-parents = <&mdss_dsi1_phy 0>,
							 <&mdss_dsi1_phy 1>;

				operating-points-v2 = <&dsi_opp_table>;
				power-domains = <&rpmpd MSM8998_VDDCX>;

				phys = <&mdss_dsi1_phy>;
				phy-names = "dsi";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dsi1_in: endpoint {
							remote-endpoint = <&dpu_intf2_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dsi1_out: endpoint {
						};
					};
				};
			};

			mdss_dsi1_phy: phy@c996400 {
				compatible = "qcom,dsi-phy-10nm-8998";
				reg = <0x0c996400 0x200>,
				      <0x0c996600 0x280>,
				      <0x0c996a00 0x10e>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
				clock-names = "iface",
					      "ref";

				#clock-cells = <1>;
				#phy-cells = <0>;

				status = "disabled";
			};
		};

		mmss_smmu: iommu@cd00000 {
			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
			reg = <0x0cd00000 0x40000>;
			#iommu-cells = <1>;

			clocks = <&mmcc MNOC_AHB_CLK>,
				 <&mmcc BIMC_SMMU_AHB_CLK>,
				 <&mmcc BIMC_SMMU_AXI_CLK>;
			clock-names = "iface-mm",
				      "iface-smmu",
				      "bus-smmu";

			#global-interrupts = <0>;
			interrupts =
				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;

			power-domains = <&mmcc BIMC_SMMU_GDSC>;
		};

		remoteproc_adsp: remoteproc@17300000 {
			compatible = "qcom,msm8998-adsp-pas";
			reg = <0x17300000 0x4040>;

			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
			clock-names = "xo";

			memory-region = <&adsp_mem>;

			qcom,smem-states = <&adsp_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			power-domains = <&rpmpd MSM8998_VDDCX>;
			power-domain-names = "cx";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
				label = "lpass";
				qcom,remote-pid = <2>;
				mboxes = <&apcs_glb 9>;
			};
		};

		apcs_glb: mailbox@17911000 {
			compatible = "qcom,msm8998-apcs-hmss-global",
				     "qcom,msm8994-apcs-kpss-global";
			reg = <0x17911000 0x1000>;

			#mbox-cells = <1>;
		};

		timer@17920000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17920000 0x1000>;

			frame@17921000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17921000 0x1000>,
				      <0x17922000 0x1000>;
			};

			frame@17923000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17923000 0x1000>;
				status = "disabled";
			};

			frame@17924000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17924000 0x1000>;
				status = "disabled";
			};

			frame@17925000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17925000 0x1000>;
				status = "disabled";
			};

			frame@17926000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17926000 0x1000>;
				status = "disabled";
			};

			frame@17927000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17927000 0x1000>;
				status = "disabled";
			};

			frame@17928000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17928000 0x1000>;
				status = "disabled";
			};
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			reg = <0x17a00000 0x10000>,       /* GICD */
			      <0x17b00000 0x100000>;      /* GICR * 8 */
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x20000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		wifi: wifi@18800000 {
			compatible = "qcom,wcn3990-wifi";
			status = "disabled";
			reg = <0x18800000 0x800000>;
			reg-names = "membase";
			memory-region = <&wlan_msa_mem>;
			clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
			clock-names = "cxo_ref_clk_pin";
			interrupts =
				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
			iommus = <&anoc2_smmu 0x1900>,
				 <&anoc2_smmu 0x1901>;
			qcom,snoc-host-cap-8bit-quirk;
		};
	};
};