tree 0775b1bd38a347f78d45faba526ac8486a09ad78
parent c5729f0b1fb8777c5dcfd2e510bc351045e9b1c4
author Liu Gang <Gang.Liu@freescale.com> 1362696062 +0000
committer Andy Fleming <afleming@freescale.com> 1367531804 -0500

powerpc/b4860qds: Add the tlb entries for SRIO interfaces

Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:

	#define CONFIG_SYS_SRIO1_MEM_VIRT   0xa0000000
	#define CONFIG_SYS_SRIO1_MEM_PHYS   0xc20000000ull

	#define CONFIG_SYS_SRIO2_MEM_VIRT   0xb0000000
	#define CONFIG_SYS_SRIO2_MEM_PHYS   0xc30000000ull

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>