&l4_wkup {						/* 0x44c00000 */
	compatible = "ti,am33xx-l4-wkup", "simple-bus";
	reg = <0x44c00000 0x800>,
	      <0x44c00800 0x800>,
	      <0x44c01000 0x400>,
	      <0x44c01400 0x400>;
	reg-names = "ap", "la", "ia0", "ia1";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x44c00000 0x100000>,	/* segment 0 */
		 <0x00100000 0x44d00000 0x100000>,	/* segment 1 */
		 <0x00200000 0x44e00000 0x100000>;	/* segment 2 */

	segment@0 {					/* 0x44c00000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
			 <0x00000800 0x00000800 0x000800>,	/* ap 1 */
			 <0x00001000 0x00001000 0x000400>,	/* ap 2 */
			 <0x00001400 0x00001400 0x000400>;	/* ap 3 */
	};

	segment@100000 {					/* 0x44d00000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00100000 0x004000>,	/* ap 4 */
			 <0x00004000 0x00104000 0x001000>,	/* ap 5 */
			 <0x00080000 0x00180000 0x002000>,	/* ap 6 */
			 <0x00082000 0x00182000 0x001000>;	/* ap 7 */

		target-module@0 {			/* 0x44d00000, ap 4 28.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x0 0x4>;
			reg-names = "rev";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x4000>;
			status = "disabled";
		};

		target-module@80000 {			/* 0x44d80000, ap 6 10.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x80000 0x2000>;
		};
	};

	segment@200000 {					/* 0x44e00000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00200000 0x002000>,	/* ap 8 */
			 <0x00002000 0x00202000 0x001000>,	/* ap 9 */
			 <0x00003000 0x00203000 0x001000>,	/* ap 10 */
			 <0x00004000 0x00204000 0x001000>,	/* ap 11 */
			 <0x00005000 0x00205000 0x001000>,	/* ap 12 */
			 <0x00006000 0x00206000 0x001000>,	/* ap 13 */
			 <0x00007000 0x00207000 0x001000>,	/* ap 14 */
			 <0x00008000 0x00208000 0x001000>,	/* ap 15 */
			 <0x00009000 0x00209000 0x001000>,	/* ap 16 */
			 <0x0000a000 0x0020a000 0x001000>,	/* ap 17 */
			 <0x0000b000 0x0020b000 0x001000>,	/* ap 18 */
			 <0x0000c000 0x0020c000 0x001000>,	/* ap 19 */
			 <0x0000d000 0x0020d000 0x001000>,	/* ap 20 */
			 <0x0000f000 0x0020f000 0x001000>,	/* ap 21 */
			 <0x00010000 0x00210000 0x010000>,	/* ap 22 */
			 <0x00020000 0x00220000 0x010000>,	/* ap 23 */
			 <0x00030000 0x00230000 0x001000>,	/* ap 24 */
			 <0x00031000 0x00231000 0x001000>,	/* ap 25 */
			 <0x00032000 0x00232000 0x001000>,	/* ap 26 */
			 <0x00033000 0x00233000 0x001000>,	/* ap 27 */
			 <0x00034000 0x00234000 0x001000>,	/* ap 28 */
			 <0x00035000 0x00235000 0x001000>,	/* ap 29 */
			 <0x00036000 0x00236000 0x001000>,	/* ap 30 */
			 <0x00037000 0x00237000 0x001000>,	/* ap 31 */
			 <0x00038000 0x00238000 0x001000>,	/* ap 32 */
			 <0x00039000 0x00239000 0x001000>,	/* ap 33 */
			 <0x0003a000 0x0023a000 0x001000>,	/* ap 34 */
			 <0x0003e000 0x0023e000 0x001000>,	/* ap 35 */
			 <0x0003f000 0x0023f000 0x001000>,	/* ap 36 */
			 <0x0000e000 0x0020e000 0x001000>,	/* ap 37 */
			 <0x00040000 0x00240000 0x040000>,	/* ap 38 */
			 <0x00080000 0x00280000 0x001000>;	/* ap 39 */

		target-module@0 {			/* 0x44e00000, ap 8 58.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0 0x4>;
			reg-names = "rev";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x2000>;

			prcm: prcm@0 {
				compatible = "ti,am3-prcm", "simple-bus";
				reg = <0 0x2000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0 0x2000>;

				prcm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				prcm_clockdomains: clockdomains {
				};
			};
		};

		target-module@3000 {			/* 0x44e03000, ap 10 0a.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x3000 0x1000>;
		};

		target-module@5000 {			/* 0x44e05000, ap 12 30.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x5000 0x1000>;
		};

		gpio0_target: target-module@7000 {	/* 0x44e07000, ap 14 20.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x7000 0x4>,
			      <0x7010 0x4>,
			      <0x7114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
				 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
			clock-names = "fck", "dbclk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x7000 0x1000>;
		};

		target-module@9000 {			/* 0x44e09000, ap 16 04.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x9050 0x4>,
			      <0x9054 0x4>,
			      <0x9058 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x9000 0x1000>;

			uart0: serial@0 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				clock-frequency = <48000000>;
				reg = <0x0 0x1000>;
				interrupts = <72>;
				status = "disabled";
				dmas = <&edma 26 0>, <&edma 27 0>;
				dma-names = "tx", "rx";
			};
		};

		target-module@b000 {			/* 0x44e0b000, ap 18 48.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xb000 0x8>,
			      <0xb010 0x8>,
			      <0xb090 0x8>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xb000 0x1000>;
		};

		target-module@d000 {			/* 0x44e0d000, ap 20 38.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0xd000 0x4>,
			      <0xd010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 0x0000d000 0x00001000>,
				 <0x00001000 0x0000e000 0x00001000>;

			tscadc: tscadc@0 {
				compatible = "ti,am3359-tscadc";
				reg = <0x0 0x1000>;
				interrupts = <16>;
				status = "disabled";
				dmas = <&edma 53 0>, <&edma 57 0>;
				dma-names = "fifo0", "fifo1";

				tsc {
					compatible = "ti,am3359-tsc";
				};
				am335x_adc: adc {
					#io-channel-cells = <1>;
					compatible = "ti,am3359-adc";
				};
			};

		};

		target-module@10000 {			/* 0x44e10000, ap 22 0c.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x10000 0x4>;
			reg-names = "rev";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 0x00010000 0x00010000>,
				 <0x00010000 0x00020000 0x00010000>;

			scm: scm@0 {
				compatible = "ti,am3-scm", "simple-bus";
				reg = <0x0 0x2000>;
				#address-cells = <1>;
				#size-cells = <1>;
				#pinctrl-cells = <1>;
				ranges = <0 0 0x2000>;

				am33xx_pinmux: pinmux@800 {
					compatible = "pinctrl-single";
					reg = <0x800 0x238>;
					#pinctrl-cells = <2>;
					pinctrl-single,register-width = <32>;
					pinctrl-single,function-mask = <0x7f>;
				};

				scm_conf: scm_conf@0 {
					compatible = "syscon", "simple-bus";
					reg = <0x0 0x800>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0 0x800>;

					phy_gmii_sel: phy-gmii-sel {
						compatible = "ti,am3352-phy-gmii-sel";
						reg = <0x650 0x4>;
						#phy-cells = <2>;
					};

					scm_clocks: clocks {
						#address-cells = <1>;
						#size-cells = <0>;
					};
				};

				wkup_m3_ipc: wkup_m3_ipc@1324 {
					compatible = "ti,am3352-wkup-m3-ipc";
					reg = <0x1324 0x24>;
					interrupts = <78>;
					ti,rproc = <&wkup_m3>;
					mboxes = <&mailbox &mbox_wkupm3>;
				};

				edma_xbar: dma-router@f90 {
					compatible = "ti,am335x-edma-crossbar";
					reg = <0xf90 0x40>;
					#dma-cells = <3>;
					dma-requests = <32>;
					dma-masters = <&edma>;
				};

				scm_clockdomains: clockdomains {
				};
			};
		};

		timer1_target: target-module@31000 {	/* 0x44e31000, ap 25 40.0 */
			compatible = "ti,sysc-omap2-timer", "ti,sysc";
			reg = <0x31000 0x4>,
			      <0x31010 0x4>,
			      <0x31014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x31000 0x1000>;

			timer1: timer@0 {
				compatible = "ti,am335x-timer-1ms";
				reg = <0x0 0x400>;
				interrupts = <67>;
				ti,timer-alwon;
				clocks = <&timer1_fck>;
				clock-names = "fck";
			};
		};

		target-module@33000 {			/* 0x44e33000, ap 27 18.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x33000 0x1000>;
		};

		target-module@35000 {			/* 0x44e35000, ap 29 50.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x35000 0x4>,
			      <0x35010 0x4>,
			      <0x35014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
					 SYSC_OMAP2_SOFTRESET)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
			clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x35000 0x1000>;
		};

		target-module@37000 {			/* 0x44e37000, ap 31 08.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x37000 0x1000>;
		};

		target-module@39000 {			/* 0x44e39000, ap 33 02.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x39000 0x1000>;
		};

		target-module@3e000 {			/* 0x44e3e000, ap 35 60.0 */
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x3e074 0x4>,
			      <0x3e078 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
			clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x3e000 0x1000>;

			rtc: rtc@0 {
				compatible = "ti,am3352-rtc", "ti,da830-rtc";
				reg = <0x0 0x1000>;
				interrupts = <75 76>;
			};
		};

		target-module@40000 {			/* 0x44e40000, ap 38 68.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x40000 0x40000>;
		};
	};
};

&l4_fw {						/* 0x47c00000 */
	compatible = "ti,am33xx-l4-fw", "simple-bus";
	reg = <0x47c00000 0x800>,
	      <0x47c00800 0x800>,
	      <0x47c01000 0x400>;
	reg-names = "ap", "la", "ia0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x47c00000 0x1000000>;	/* segment 0 */

	segment@0 {					/* 0x47c00000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
			 <0x00000800 0x00000800 0x000800>,	/* ap 1 */
			 <0x00001000 0x00001000 0x000400>,	/* ap 2 */
			 <0x0000c000 0x0000c000 0x001000>,	/* ap 3 */
			 <0x0000d000 0x0000d000 0x001000>,	/* ap 4 */
			 <0x0000e000 0x0000e000 0x001000>,	/* ap 5 */
			 <0x0000f000 0x0000f000 0x001000>,	/* ap 6 */
			 <0x00010000 0x00010000 0x001000>,	/* ap 7 */
			 <0x00011000 0x00011000 0x001000>,	/* ap 8 */
			 <0x0001a000 0x0001a000 0x001000>,	/* ap 9 */
			 <0x0001b000 0x0001b000 0x001000>,	/* ap 10 */
			 <0x00024000 0x00024000 0x001000>,	/* ap 11 */
			 <0x00025000 0x00025000 0x001000>,	/* ap 12 */
			 <0x00026000 0x00026000 0x001000>,	/* ap 13 */
			 <0x00027000 0x00027000 0x001000>,	/* ap 14 */
			 <0x00030000 0x00030000 0x001000>,	/* ap 15 */
			 <0x00031000 0x00031000 0x001000>,	/* ap 16 */
			 <0x00038000 0x00038000 0x001000>,	/* ap 17 */
			 <0x00039000 0x00039000 0x001000>,	/* ap 18 */
			 <0x0003a000 0x0003a000 0x001000>,	/* ap 19 */
			 <0x0003b000 0x0003b000 0x001000>,	/* ap 20 */
			 <0x0003e000 0x0003e000 0x001000>,	/* ap 21 */
			 <0x0003f000 0x0003f000 0x001000>,	/* ap 22 */
			 <0x0003c000 0x0003c000 0x001000>,	/* ap 23 */
			 <0x00040000 0x00040000 0x001000>,	/* ap 24 */
			 <0x00046000 0x00046000 0x001000>,	/* ap 25 */
			 <0x00047000 0x00047000 0x001000>,	/* ap 26 */
			 <0x00044000 0x00044000 0x001000>,	/* ap 27 */
			 <0x00045000 0x00045000 0x001000>,	/* ap 28 */
			 <0x00028000 0x00028000 0x001000>,	/* ap 29 */
			 <0x00029000 0x00029000 0x001000>,	/* ap 30 */
			 <0x00032000 0x00032000 0x001000>,	/* ap 31 */
			 <0x00033000 0x00033000 0x001000>,	/* ap 32 */
			 <0x0003d000 0x0003d000 0x001000>,	/* ap 33 */
			 <0x00041000 0x00041000 0x001000>,	/* ap 34 */
			 <0x00042000 0x00042000 0x001000>,	/* ap 35 */
			 <0x00043000 0x00043000 0x001000>,	/* ap 36 */
			 <0x00014000 0x00014000 0x001000>,	/* ap 37 */
			 <0x00015000 0x00015000 0x001000>;	/* ap 38 */

		target-module@c000 {			/* 0x47c0c000, ap 3 04.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xc000 0x1000>;
		};

		target-module@e000 {			/* 0x47c0e000, ap 5 0c.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe000 0x1000>;
		};

		target-module@10000 {			/* 0x47c10000, ap 7 20.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x10000 0x1000>;
		};

		target-module@14000 {			/* 0x47c14000, ap 37 3c.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x14000 0x1000>;
		};

		target-module@1a000 {			/* 0x47c1a000, ap 9 08.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x1a000 0x1000>;
		};

		target-module@24000 {			/* 0x47c24000, ap 11 28.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x24000 0x1000>;
		};

		target-module@26000 {			/* 0x47c26000, ap 13 30.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x1000>;
		};

		target-module@28000 {			/* 0x47c28000, ap 29 40.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x28000 0x1000>;
		};

		target-module@30000 {			/* 0x47c30000, ap 15 14.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x30000 0x1000>;
		};

		target-module@32000 {			/* 0x47c32000, ap 31 06.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x32000 0x1000>;
		};

		target-module@38000 {			/* 0x47c38000, ap 17 18.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x38000 0x1000>;
		};

		target-module@3a000 {			/* 0x47c3a000, ap 19 1c.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x3a000 0x1000>;
		};

		target-module@3c000 {			/* 0x47c3c000, ap 23 38.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x3c000 0x1000>;
		};

		target-module@3e000 {			/* 0x47c3e000, ap 21 10.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x3e000 0x1000>;
		};

		target-module@40000 {			/* 0x47c40000, ap 24 02.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x40000 0x1000>;
		};

		target-module@42000 {			/* 0x47c42000, ap 35 34.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x42000 0x1000>;
		};

		target-module@44000 {			/* 0x47c44000, ap 27 24.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x44000 0x1000>;
		};

		target-module@46000 {			/* 0x47c46000, ap 25 2c.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x46000 0x1000>;
		};
	};
};

&l4_fast {					/* 0x4a000000 */
	compatible = "ti,am33xx-l4-fast", "simple-bus";
	reg = <0x4a000000 0x800>,
	      <0x4a000800 0x800>,
	      <0x4a001000 0x400>;
	reg-names = "ap", "la", "ia0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4a000000 0x1000000>;	/* segment 0 */

	segment@0 {					/* 0x4a000000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
			 <0x00000800 0x00000800 0x000800>,	/* ap 1 */
			 <0x00001000 0x00001000 0x000400>,	/* ap 2 */
			 <0x00100000 0x00100000 0x008000>,	/* ap 3 */
			 <0x00108000 0x00108000 0x001000>,	/* ap 4 */
			 <0x00180000 0x00180000 0x020000>,	/* ap 5 */
			 <0x001a0000 0x001a0000 0x001000>,	/* ap 6 */
			 <0x00200000 0x00200000 0x080000>,	/* ap 7 */
			 <0x00280000 0x00280000 0x001000>,	/* ap 8 */
			 <0x00300000 0x00300000 0x080000>,	/* ap 9 */
			 <0x00380000 0x00380000 0x001000>;	/* ap 10 */

		target-module@100000 {			/* 0x4a100000, ap 3 08.0 */
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x101200 0x4>,
			      <0x101208 0x4>,
			      <0x101204 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <0>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>;
			ti,syss-mask = <1>;
			clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x100000 0x8000>;
		};

		target-module@180000 {			/* 0x4a180000, ap 5 10.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x180000 0x20000>;
		};

		target-module@200000 {			/* 0x4a200000, ap 7 02.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x200000 0x80000>;
		};

		pruss_tm: target-module@300000 {	/* 0x4a300000, ap 9 04.0 */
			compatible = "ti,sysc-pruss", "ti,sysc";
			reg = <0x326000 0x4>,
			      <0x326004 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
					 SYSC_PRUSS_SUB_MWAIT)>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
			clock-names = "fck";
			resets = <&prm_per 1>;
			reset-names = "rstctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x300000 0x80000>;
			status = "disabled";
		};
	};
};

&l4_mpuss {						/* 0x4b140000 */
	compatible = "ti,am33xx-l4-mpuss", "simple-bus";
	reg = <0x4b144400 0x100>,
	      <0x4b144800 0x400>;
	reg-names = "la", "ap";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x4b140000 0x008000>;	/* segment 0 */

	segment@0 {					/* 0x4b140000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00004800 0x00004800 0x000400>,	/* ap 0 */
			 <0x00001000 0x00001000 0x001000>,	/* ap 1 */
			 <0x00002000 0x00002000 0x001000>,	/* ap 2 */
			 <0x00004000 0x00004000 0x000400>,	/* ap 3 */
			 <0x00005000 0x00005000 0x000400>,	/* ap 4 */
			 <0x00000000 0x00000000 0x001000>,	/* ap 5 */
			 <0x00003000 0x00003000 0x001000>,	/* ap 6 */
			 <0x00000800 0x00000800 0x000800>;	/* ap 7 */

		target-module@0 {			/* 0x4b140000, ap 5 02.2 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 0x00000000 0x00001000>,
				 <0x00001000 0x00001000 0x00001000>,
				 <0x00002000 0x00002000 0x00001000>;
		};

		target-module@3000 {			/* 0x4b143000, ap 6 04.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x3000 0x1000>;
		};
	};
};

&l4_per {						/* 0x48000000 */
	compatible = "ti,am33xx-l4-per", "simple-bus";
	reg = <0x48000000 0x800>,
	      <0x48000800 0x800>,
	      <0x48001000 0x400>,
	      <0x48001400 0x400>,
	      <0x48001800 0x400>,
	      <0x48001c00 0x400>;
	reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x00000000 0x48000000 0x100000>,	/* segment 0 */
		 <0x00100000 0x48100000 0x100000>,	/* segment 1 */
		 <0x00200000 0x48200000 0x100000>,	/* segment 2 */
		 <0x00300000 0x48300000 0x100000>,	/* segment 3 */
		 <0x46000000 0x46000000 0x400000>,	/* l3 data port */
		 <0x46400000 0x46400000 0x400000>;	/* l3 data port */

	segment@0 {					/* 0x48000000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
			 <0x00000800 0x00000800 0x000800>,	/* ap 1 */
			 <0x00001000 0x00001000 0x000400>,	/* ap 2 */
			 <0x00001400 0x00001400 0x000400>,	/* ap 3 */
			 <0x00001800 0x00001800 0x000400>,	/* ap 4 */
			 <0x00001c00 0x00001c00 0x000400>,	/* ap 5 */
			 <0x00008000 0x00008000 0x001000>,	/* ap 6 */
			 <0x00009000 0x00009000 0x001000>,	/* ap 7 */
			 <0x00016000 0x00016000 0x001000>,	/* ap 8 */
			 <0x00017000 0x00017000 0x001000>,	/* ap 9 */
			 <0x00022000 0x00022000 0x001000>,	/* ap 10 */
			 <0x00023000 0x00023000 0x001000>,	/* ap 11 */
			 <0x00024000 0x00024000 0x001000>,	/* ap 12 */
			 <0x00025000 0x00025000 0x001000>,	/* ap 13 */
			 <0x0002a000 0x0002a000 0x001000>,	/* ap 14 */
			 <0x0002b000 0x0002b000 0x001000>,	/* ap 15 */
			 <0x00038000 0x00038000 0x002000>,	/* ap 16 */
			 <0x0003a000 0x0003a000 0x001000>,	/* ap 17 */
			 <0x00014000 0x00014000 0x001000>,	/* ap 18 */
			 <0x00015000 0x00015000 0x001000>,	/* ap 19 */
			 <0x0003c000 0x0003c000 0x002000>,	/* ap 20 */
			 <0x0003e000 0x0003e000 0x001000>,	/* ap 21 */
			 <0x00040000 0x00040000 0x001000>,	/* ap 22 */
			 <0x00041000 0x00041000 0x001000>,	/* ap 23 */
			 <0x00042000 0x00042000 0x001000>,	/* ap 24 */
			 <0x00043000 0x00043000 0x001000>,	/* ap 25 */
			 <0x00044000 0x00044000 0x001000>,	/* ap 26 */
			 <0x00045000 0x00045000 0x001000>,	/* ap 27 */
			 <0x00046000 0x00046000 0x001000>,	/* ap 28 */
			 <0x00047000 0x00047000 0x001000>,	/* ap 29 */
			 <0x00048000 0x00048000 0x001000>,	/* ap 30 */
			 <0x00049000 0x00049000 0x001000>,	/* ap 31 */
			 <0x0004c000 0x0004c000 0x001000>,	/* ap 32 */
			 <0x0004d000 0x0004d000 0x001000>,	/* ap 33 */
			 <0x00050000 0x00050000 0x002000>,	/* ap 34 */
			 <0x00052000 0x00052000 0x001000>,	/* ap 35 */
			 <0x00060000 0x00060000 0x001000>,	/* ap 36 */
			 <0x00061000 0x00061000 0x001000>,	/* ap 37 */
			 <0x00080000 0x00080000 0x010000>,	/* ap 38 */
			 <0x00090000 0x00090000 0x001000>,	/* ap 39 */
			 <0x000a0000 0x000a0000 0x010000>,	/* ap 40 */
			 <0x000b0000 0x000b0000 0x001000>,	/* ap 41 */
			 <0x00030000 0x00030000 0x001000>,	/* ap 77 */
			 <0x00031000 0x00031000 0x001000>,	/* ap 78 */
			 <0x0004a000 0x0004a000 0x001000>,	/* ap 85 */
			 <0x0004b000 0x0004b000 0x001000>,	/* ap 86 */
			 <0x000c8000 0x000c8000 0x001000>,	/* ap 87 */
			 <0x000c9000 0x000c9000 0x001000>,	/* ap 88 */
			 <0x000cc000 0x000cc000 0x001000>,	/* ap 89 */
			 <0x000cd000 0x000cd000 0x001000>,	/* ap 90 */
			 <0x000ca000 0x000ca000 0x001000>,	/* ap 91 */
			 <0x000cb000 0x000cb000 0x001000>,	/* ap 92 */
			 <0x46000000 0x46000000 0x400000>,	/* l3 data port */
			 <0x46400000 0x46400000 0x400000>;	/* l3 data port */

		target-module@8000 {			/* 0x48008000, ap 6 10.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x8000 0x1000>;
		};

		target-module@14000 {			/* 0x48014000, ap 18 58.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x14000 0x1000>;
		};

		target-module@16000 {			/* 0x48016000, ap 8 3c.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x16000 0x1000>;
		};

		target-module@22000 {			/* 0x48022000, ap 10 12.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x22050 0x4>,
			      <0x22054 0x4>,
			      <0x22058 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x22000 0x1000>;

			uart1: serial@0 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				clock-frequency = <48000000>;
				reg = <0x0 0x1000>;
				interrupts = <73>;
				status = "disabled";
				dmas = <&edma 28 0>, <&edma 29 0>;
				dma-names = "tx", "rx";
			};
		};

		target-module@24000 {			/* 0x48024000, ap 12 14.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x24050 0x4>,
			      <0x24054 0x4>,
			      <0x24058 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x24000 0x1000>;

			uart2: serial@0 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				clock-frequency = <48000000>;
				reg = <0x0 0x1000>;
				interrupts = <74>;
				status = "disabled";
				dmas = <&edma 30 0>, <&edma 31 0>;
				dma-names = "tx", "rx";
			};
		};

		target-module@2a000 {			/* 0x4802a000, ap 14 2a.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x2a000 0x8>,
			      <0x2a010 0x8>,
			      <0x2a090 0x8>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2a000 0x1000>;
		};

		target-module@30000 {			/* 0x48030000, ap 77 08.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x30000 0x4>,
			      <0x30110 0x4>,
			      <0x30114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x30000 0x1000>;

			spi0: spi@0 {
				compatible = "ti,omap4-mcspi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x0 0x400>;
				interrupts = <65>;
				ti,spi-num-cs = <2>;
				dmas = <&edma 16 0
					&edma 17 0
					&edma 18 0
					&edma 19 0>;
				dma-names = "tx0", "rx0", "tx1", "rx1";
				status = "disabled";
			};
		};

		target-module@38000 {			/* 0x48038000, ap 16 02.0 */
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x38000 0x4>,
			      <0x38004 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			/* Domains (P, C): per_pwrdm, l3s_clkdm */
			clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x38000 0x2000>,
				 <0x46000000 0x46000000 0x400000>;

			mcasp0: mcasp@0 {
				compatible = "ti,am33xx-mcasp-audio";
				reg = <0x0 0x2000>,
				      <0x46000000 0x400000>;
				reg-names = "mpu", "dat";
				interrupts = <80>, <81>;
				interrupt-names = "tx", "rx";
				status = "disabled";
				dmas = <&edma 8 2>,
					<&edma 9 2>;
				dma-names = "tx", "rx";
			};
		};

		target-module@3c000 {			/* 0x4803c000, ap 20 32.0 */
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x3c000 0x4>,
			      <0x3c004 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			/* Domains (P, C): per_pwrdm, l3s_clkdm */
			clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x3c000 0x2000>,
				 <0x46400000 0x46400000 0x400000>;

			mcasp1: mcasp@0 {
				compatible = "ti,am33xx-mcasp-audio";
				reg = <0x0 0x2000>,
				      <0x46400000 0x400000>;
				reg-names = "mpu", "dat";
				interrupts = <82>, <83>;
				interrupt-names = "tx", "rx";
				status = "disabled";
				dmas = <&edma 10 2>,
					<&edma 11 2>;
				dma-names = "tx", "rx";
			};
		};

		timer2_target: target-module@40000 {	/* 0x48040000, ap 22 1e.0 */
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x40000 0x4>,
			      <0x40010 0x4>,
			      <0x40014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x40000 0x1000>;

			timer2: timer@0 {
				compatible = "ti,am335x-timer";
				reg = <0x0 0x400>;
				interrupts = <68>;
				clocks = <&timer2_fck>;
				clock-names = "fck";
			};
		};

		target-module@42000 {			/* 0x48042000, ap 24 1c.0 */
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x42000 0x4>,
			      <0x42010 0x4>,
			      <0x42014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x42000 0x1000>;

			timer3: timer@0 {
				compatible = "ti,am335x-timer";
				reg = <0x0 0x400>;
				interrupts = <69>;
			};
		};

		target-module@44000 {			/* 0x48044000, ap 26 26.0 */
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x44000 0x4>,
			      <0x44010 0x4>,
			      <0x44014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x44000 0x1000>;

			timer4: timer@0 {
				compatible = "ti,am335x-timer";
				reg = <0x0 0x400>;
				interrupts = <92>;
				ti,timer-pwm;
			};
		};

		target-module@46000 {			/* 0x48046000, ap 28 28.0 */
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x46000 0x4>,
			      <0x46010 0x4>,
			      <0x46014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x46000 0x1000>;

			timer5: timer@0 {
				compatible = "ti,am335x-timer";
				reg = <0x0 0x400>;
				interrupts = <93>;
				ti,timer-pwm;
			};
		};

		target-module@48000 {			/* 0x48048000, ap 30 22.0 */
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x48000 0x4>,
			      <0x48010 0x4>,
			      <0x48014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x48000 0x1000>;

			timer6: timer@0 {
				compatible = "ti,am335x-timer";
				reg = <0x0 0x400>;
				interrupts = <94>;
				ti,timer-pwm;
			};
		};

		target-module@4a000 {			/* 0x4804a000, ap 85 60.0 */
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x4a000 0x4>,
			      <0x4a010 0x4>,
			      <0x4a014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4a000 0x1000>;

			timer7: timer@0 {
				compatible = "ti,am335x-timer";
				reg = <0x0 0x400>;
				interrupts = <95>;
				ti,timer-pwm;
			};
		};

		target-module@4c000 {			/* 0x4804c000, ap 32 36.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x4c000 0x4>,
			      <0x4c010 0x4>,
			      <0x4c114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
				 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
			clock-names = "fck", "dbclk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4c000 0x1000>;
		};

		target-module@50000 {			/* 0x48050000, ap 34 2c.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x50000 0x2000>;
		};

		target-module@60000 {			/* 0x48060000, ap 36 0c.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x602fc 0x4>,
			      <0x60110 0x4>,
			      <0x60114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x60000 0x1000>;
		};

		target-module@80000 {			/* 0x48080000, ap 38 18.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x80000 0x4>,
			      <0x80010 0x4>,
			      <0x80014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x80000 0x10000>;

			elm: elm@0 {
				compatible = "ti,am3352-elm";
				reg = <0x0 0x2000>;
				interrupts = <4>;
				status = "disabled";
			};
		};

		target-module@a0000 {			/* 0x480a0000, ap 40 5e.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xa0000 0x10000>;
		};

		target-module@c8000 {			/* 0x480c8000, ap 87 06.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0xc8000 0x4>,
			      <0xc8010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xc8000 0x1000>;

			mailbox: mailbox@0 {
				compatible = "ti,omap4-mailbox";
				reg = <0x0 0x200>;
				interrupts = <77>;
				#mbox-cells = <1>;
				ti,mbox-num-users = <4>;
				ti,mbox-num-fifos = <8>;
				mbox_wkupm3: wkup_m3 {
					ti,mbox-send-noirq;
					ti,mbox-tx = <0 0 0>;
					ti,mbox-rx = <0 0 3>;
				};
			};
		};

		target-module@ca000 {			/* 0x480ca000, ap 91 40.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xca000 0x4>,
			      <0xca010 0x4>,
			      <0xca014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xca000 0x1000>;

			hwspinlock: spinlock@0 {
				compatible = "ti,omap4-hwspinlock";
				reg = <0x0 0x1000>;
				#hwlock-cells = <1>;
			};
		};

		target-module@cc000 {			/* 0x480cc000, ap 89 0e.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xcc000 0x1000>;
		};
	};

	segment@100000 {					/* 0x48100000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0008c000 0x0018c000 0x001000>,	/* ap 42 */
			 <0x0008d000 0x0018d000 0x001000>,	/* ap 43 */
			 <0x0008e000 0x0018e000 0x001000>,	/* ap 44 */
			 <0x0008f000 0x0018f000 0x001000>,	/* ap 45 */
			 <0x0009c000 0x0019c000 0x001000>,	/* ap 46 */
			 <0x0009d000 0x0019d000 0x001000>,	/* ap 47 */
			 <0x000a6000 0x001a6000 0x001000>,	/* ap 48 */
			 <0x000a7000 0x001a7000 0x001000>,	/* ap 49 */
			 <0x000a8000 0x001a8000 0x001000>,	/* ap 50 */
			 <0x000a9000 0x001a9000 0x001000>,	/* ap 51 */
			 <0x000aa000 0x001aa000 0x001000>,	/* ap 52 */
			 <0x000ab000 0x001ab000 0x001000>,	/* ap 53 */
			 <0x000ac000 0x001ac000 0x001000>,	/* ap 54 */
			 <0x000ad000 0x001ad000 0x001000>,	/* ap 55 */
			 <0x000ae000 0x001ae000 0x001000>,	/* ap 56 */
			 <0x000af000 0x001af000 0x001000>,	/* ap 57 */
			 <0x000b0000 0x001b0000 0x010000>,	/* ap 58 */
			 <0x000c0000 0x001c0000 0x001000>,	/* ap 59 */
			 <0x000cc000 0x001cc000 0x002000>,	/* ap 60 */
			 <0x000ce000 0x001ce000 0x002000>,	/* ap 61 */
			 <0x000d0000 0x001d0000 0x002000>,	/* ap 62 */
			 <0x000d2000 0x001d2000 0x002000>,	/* ap 63 */
			 <0x000d8000 0x001d8000 0x001000>,	/* ap 64 */
			 <0x000d9000 0x001d9000 0x001000>,	/* ap 65 */
			 <0x000a0000 0x001a0000 0x001000>,	/* ap 79 */
			 <0x000a1000 0x001a1000 0x001000>,	/* ap 80 */
			 <0x000a2000 0x001a2000 0x001000>,	/* ap 81 */
			 <0x000a3000 0x001a3000 0x001000>,	/* ap 82 */
			 <0x000a4000 0x001a4000 0x001000>,	/* ap 83 */
			 <0x000a5000 0x001a5000 0x001000>;	/* ap 84 */

		target-module@8c000 {			/* 0x4818c000, ap 42 04.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x8c000 0x1000>;
		};

		target-module@8e000 {			/* 0x4818e000, ap 44 0a.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x8e000 0x1000>;
		};

		target-module@9c000 {			/* 0x4819c000, ap 46 5a.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x9c000 0x8>,
			      <0x9c010 0x8>,
			      <0x9c090 0x8>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x9c000 0x1000>;
		};

		target-module@a0000 {			/* 0x481a0000, ap 79 24.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xa0000 0x4>,
			      <0xa0110 0x4>,
			      <0xa0114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xa0000 0x1000>;

			spi1: spi@0 {
				compatible = "ti,omap4-mcspi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x0 0x400>;
				interrupts = <125>;
				ti,spi-num-cs = <2>;
				dmas = <&edma 42 0
					&edma 43 0
					&edma 44 0
					&edma 45 0>;
				dma-names = "tx0", "rx0", "tx1", "rx1";
				status = "disabled";
			};
		};

		target-module@a2000 {			/* 0x481a2000, ap 81 2e.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xa2000 0x1000>;
		};

		target-module@a4000 {			/* 0x481a4000, ap 83 30.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xa4000 0x1000>;
		};

		target-module@a6000 {			/* 0x481a6000, ap 48 16.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xa6050 0x4>,
			      <0xa6054 0x4>,
			      <0xa6058 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xa6000 0x1000>;

			uart3: serial@0 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				clock-frequency = <48000000>;
				reg = <0x0 0x1000>;
				interrupts = <44>;
				status = "disabled";
			};
		};

		target-module@a8000 {			/* 0x481a8000, ap 50 20.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xa8050 0x4>,
			      <0xa8054 0x4>,
			      <0xa8058 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xa8000 0x1000>;

			uart4: serial@0 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				clock-frequency = <48000000>;
				reg = <0x0 0x1000>;
				interrupts = <45>;
				status = "disabled";
			};
		};

		target-module@aa000 {			/* 0x481aa000, ap 52 1a.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xaa050 0x4>,
			      <0xaa054 0x4>,
			      <0xaa058 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xaa000 0x1000>;

			uart5: serial@0 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				clock-frequency = <48000000>;
				reg = <0x0 0x1000>;
				interrupts = <46>;
				status = "disabled";
			};
		};

		target-module@ac000 {			/* 0x481ac000, ap 54 38.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xac000 0x4>,
			      <0xac010 0x4>,
			      <0xac114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
				 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
			clock-names = "fck", "dbclk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xac000 0x1000>;
		};

		target-module@ae000 {			/* 0x481ae000, ap 56 3a.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xae000 0x4>,
			      <0xae010 0x4>,
			      <0xae114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
				 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
			clock-names = "fck", "dbclk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xae000 0x1000>;
		};

		target-module@b0000 {			/* 0x481b0000, ap 58 50.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xb0000 0x10000>;
		};

		target-module@cc000 {			/* 0x481cc000, ap 60 46.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0xcc020 0x4>;
			reg-names = "rev";
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
				 <&dcan0_fck>;
			clock-names = "fck", "osc";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xcc000 0x2000>;

			dcan0: can@0 {
				compatible = "ti,am3352-d_can";
				reg = <0x0 0x2000>;
				clocks = <&dcan0_fck>;
				clock-names = "fck";
				syscon-raminit = <&scm_conf 0x644 0>;
				interrupts = <52>;
				status = "disabled";
			};
		};

		target-module@d0000 {			/* 0x481d0000, ap 62 42.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0xd0020 0x4>;
			reg-names = "rev";
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
				 <&dcan1_fck>;
			clock-names = "fck", "osc";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xd0000 0x2000>;

			dcan1: can@0 {
				compatible = "ti,am3352-d_can";
				reg = <0x0 0x2000>;
				clocks = <&dcan1_fck>;
				clock-names = "fck";
				syscon-raminit = <&scm_conf 0x644 1>;
				interrupts = <55>;
				status = "disabled";
			};
		};

		target-module@d8000 {			/* 0x481d8000, ap 64 66.0 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0xd82fc 0x4>,
			      <0xd8110 0x4>,
			      <0xd8114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xd8000 0x1000>;
		};
	};

	segment@200000 {					/* 0x48200000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
	};

	segment@300000 {					/* 0x48300000 */
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00300000 0x001000>,	/* ap 66 */
			 <0x00001000 0x00301000 0x001000>,	/* ap 67 */
			 <0x00002000 0x00302000 0x001000>,	/* ap 68 */
			 <0x00003000 0x00303000 0x001000>,	/* ap 69 */
			 <0x00004000 0x00304000 0x001000>,	/* ap 70 */
			 <0x00005000 0x00305000 0x001000>,	/* ap 71 */
			 <0x0000e000 0x0030e000 0x001000>,	/* ap 72 */
			 <0x0000f000 0x0030f000 0x001000>,	/* ap 73 */
			 <0x00018000 0x00318000 0x004000>,	/* ap 74 */
			 <0x0001c000 0x0031c000 0x001000>,	/* ap 75 */
			 <0x00010000 0x00310000 0x002000>,	/* ap 76 */
			 <0x00012000 0x00312000 0x001000>,	/* ap 93 */
			 <0x00015000 0x00315000 0x001000>,	/* ap 94 */
			 <0x00016000 0x00316000 0x001000>,	/* ap 95 */
			 <0x00017000 0x00317000 0x001000>,	/* ap 96 */
			 <0x00013000 0x00313000 0x001000>,	/* ap 97 */
			 <0x00014000 0x00314000 0x001000>,	/* ap 98 */
			 <0x00020000 0x00320000 0x001000>,	/* ap 99 */
			 <0x00021000 0x00321000 0x001000>,	/* ap 100 */
			 <0x00022000 0x00322000 0x001000>,	/* ap 101 */
			 <0x00023000 0x00323000 0x001000>,	/* ap 102 */
			 <0x00024000 0x00324000 0x001000>,	/* ap 103 */
			 <0x00025000 0x00325000 0x001000>;	/* ap 104 */

		target-module@0 {			/* 0x48300000, ap 66 48.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x0 0x4>,
			      <0x4 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1000>;

			epwmss0: epwmss@0 {
				compatible = "ti,am33xx-pwmss";
				reg = <0x0 0x10>;
				#address-cells = <1>;
				#size-cells = <1>;
				status = "disabled";
				ranges = <0 0 0x1000>;

				ecap0: ecap@100 {
					compatible = "ti,am3352-ecap",
						     "ti,am33xx-ecap";
					#pwm-cells = <3>;
					reg = <0x100 0x80>;
					clocks = <&l4ls_gclk>;
					clock-names = "fck";
					interrupts = <31>;
					interrupt-names = "ecap0";
					status = "disabled";
				};

				ehrpwm0: pwm@200 {
					compatible = "ti,am3352-ehrpwm",
						     "ti,am33xx-ehrpwm";
					#pwm-cells = <3>;
					reg = <0x200 0x80>;
					clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
					clock-names = "tbclk", "fck";
					status = "disabled";
				};
			};
		};

		target-module@2000 {			/* 0x48302000, ap 68 52.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x2000 0x4>,
			      <0x2004 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x2000 0x1000>;

			epwmss1: epwmss@0 {
				compatible = "ti,am33xx-pwmss";
				reg = <0x0 0x10>;
				#address-cells = <1>;
				#size-cells = <1>;
				status = "disabled";
				ranges = <0 0 0x1000>;

				ecap1: ecap@100 {
					compatible = "ti,am3352-ecap",
						     "ti,am33xx-ecap";
					#pwm-cells = <3>;
					reg = <0x100 0x80>;
					clocks = <&l4ls_gclk>;
					clock-names = "fck";
					interrupts = <47>;
					interrupt-names = "ecap1";
					status = "disabled";
				};

				ehrpwm1: pwm@200 {
					compatible = "ti,am3352-ehrpwm",
						     "ti,am33xx-ehrpwm";
					#pwm-cells = <3>;
					reg = <0x200 0x80>;
					clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
					clock-names = "tbclk", "fck";
					status = "disabled";
				};
			};
		};

		target-module@4000 {			/* 0x48304000, ap 70 44.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x4000 0x4>,
			      <0x4004 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4000 0x1000>;

			epwmss2: epwmss@0 {
				compatible = "ti,am33xx-pwmss";
				reg = <0x0 0x10>;
				#address-cells = <1>;
				#size-cells = <1>;
				status = "disabled";
				ranges = <0 0 0x1000>;

				ecap2: ecap@100 {
					compatible = "ti,am3352-ecap",
						     "ti,am33xx-ecap";
					#pwm-cells = <3>;
					reg = <0x100 0x80>;
					clocks = <&l4ls_gclk>;
					clock-names = "fck";
					interrupts = <61>;
					interrupt-names = "ecap2";
					status = "disabled";
				};

				ehrpwm2: pwm@200 {
					compatible = "ti,am3352-ehrpwm",
						     "ti,am33xx-ehrpwm";
					#pwm-cells = <3>;
					reg = <0x200 0x80>;
					clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
					clock-names = "tbclk", "fck";
					status = "disabled";
				};
			};
		};

		target-module@e000 {			/* 0x4830e000, ap 72 4a.0 */
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0xe000 0x4>,
			      <0xe054 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			/* Domains (P, C): per_pwrdm, lcdc_clkdm */
			clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe000 0x1000>;

			lcdc: lcdc@0 {
				compatible = "ti,am33xx-tilcdc";
				reg = <0x0 0x1000>;
				interrupts = <36>;
				status = "disabled";
			};
		};

		target-module@10000 {			/* 0x48310000, ap 76 4e.1 */
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x11fe0 0x4>,
			      <0x11fe4 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>;
			/* Domains (P, C): per_pwrdm, l4ls_clkdm */
			clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x10000 0x2000>;

			rng: rng@0 {
				compatible = "ti,omap4-rng";
				reg = <0x0 0x2000>;
				interrupts = <111>;
			};
		};

		target-module@13000 {			/* 0x48313000, ap 97 62.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x13000 0x1000>;
		};

		target-module@15000 {			/* 0x48315000, ap 94 56.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 0x00015000 0x00001000>,
				 <0x00001000 0x00016000 0x00001000>;
		};

		target-module@18000 {			/* 0x48318000, ap 74 4c.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x18000 0x4000>;
		};

		target-module@20000 {			/* 0x48320000, ap 99 34.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x20000 0x1000>;
		};

		target-module@22000 {			/* 0x48322000, ap 101 3e.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x22000 0x1000>;
		};

		target-module@24000 {			/* 0x48324000, ap 103 68.0 */
			compatible = "ti,sysc";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x24000 0x1000>;
		};
	};
};