// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) 2019
 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
 */

/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-evk-u-boot.dtsi"
#include <dt-bindings/pinctrl/pins-imxrt1050.h>

/ {
	model = "NXP IMXRT1050-evk board";
	compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";

	chosen {
		bootargs = "root=/dev/ram";
		stdout-path = "serial0:115200n8";
	};

	memory {
		reg = <0x80000000 0x2000000>;
	};
};

&lpuart1 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	status = "okay";
};

&semc {
	/*
	 * Memory configuration from sdram datasheet IS42S16160J-6BLI
	 */
	fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
				MUX_CSX0_SDRAM_CS1
				0
				0
				0
				0>;
	fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
					BL_8
					COL_9BITS
					CL_3>;
	fsl,sdram-timing = /bits/ 8 <0x2
				     0x2
				     0x9
				     0x1
				     0x5
				     0x6

				     0x20
				     0x09
				     0x01
				     0x00

				     0x04
				     0x0A
				     0x21
				     0x50>;

	bank1: bank@0 {
		fsl,base-address = <0x80000000>;
		fsl,memory-size = <MEM_SIZE_32M>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;

	imxrt1050-evk {
		pinctrl_lpuart1: lpuart1grp {
			fsl,pins = <
				MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
					0xf1
				MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
					0xf1
			>;
		};

		pinctrl_semc: semcgrp {
			fsl,pins = <
				MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
					0xf1	/* SEMC_D0 */
				MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
					0xf1	/* SEMC_D1 */
				MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
					0xf1	/* SEMC_D2 */
				MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
					0xf1	/* SEMC_D3 */
				MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
					0xf1	/* SEMC_D4 */
				MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
					0xf1	/* SEMC_D5 */
				MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
					0xf1	/* SEMC_D6 */
				MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
					0xf1	/* SEMC_D7 */
				MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
					0xf1	/* SEMC_DM0 */
				MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
					0xf1	/* SEMC_A0 */
				MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
					0xf1	/* SEMC_A1 */
				MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
					0xf1	/* SEMC_A2 */
				MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
					0xf1	/* SEMC_A3 */
				MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
					0xf1	/* SEMC_A4 */
				MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
					0xf1	/* SEMC_A5 */
				MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
					0xf1	/* SEMC_A6 */
				MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
					0xf1	/* SEMC_A7 */
				MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
					0xf1	/* SEMC_A8 */
				MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
					0xf1	/* SEMC_A9 */
				MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
					0xf1	/* SEMC_A11 */
				MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
					0xf1	/* SEMC_A12 */
				MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
					0xf1	/* SEMC_BA0 */
				MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
					0xf1	/* SEMC_BA1 */
				MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
					0xf1	/* SEMC_A10 */
				MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
					0xf1	/* SEMC_CAS */
				MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
					0xf1	/* SEMC_RAS */
				MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
					0xf1	/* SEMC_CLK */
				MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
					0xf1	/* SEMC_CKE */
				MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
					0xf1	/* SEMC_WE */
				MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
					0xf1	/* SEMC_CS0 */
				MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
					0xf1	/* SEMC_D8 */
				MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
					0xf1	/* SEMC_D9 */
				MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
					0xf1	/* SEMC_D10 */
				MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
					0xf1	/* SEMC_D11 */
				MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
					0xf1	/* SEMC_D12 */
				MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
					0xf1	/* SEMC_D13 */
				MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
					0xf1	/* SEMC_D14 */
				MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
					0xf1	/* SEMC_D15 */
				MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
					0xf1	/* SEMC_DM1 */
				MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
					(IMX_PAD_SION | 0xf1)	/* SEMC_DQS */
			>;
		};

		pinctrl_usdhc0: usdhc0grp {
			fsl,pins = <
				MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
					0x1B000
				MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
					0xB069
				MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
					0x17061
				MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
					0x17061
				MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
					0x17061
				MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
					0x17061
				MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
					0x17061
				MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
					0x17061
			>;
		};
	};
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc0>;
	pinctrl-1 = <&pinctrl_usdhc0>;
	pinctrl-2 = <&pinctrl_usdhc0>;
	pinctrl-3 = <&pinctrl_usdhc0>;
	status = "okay";

	cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};