// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019, 2021 NXP
 */

#include "imx8mm-u-boot.dtsi"

/ {
	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog1>;
		bootph-pre-ram;
	};
};

&aips4 {
	bootph-pre-ram;
};

&reg_usdhc2_vmmc {
	u-boot,off-on-delay-us = <20000>;
};

&pinctrl_reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&pinctrl_uart2 {
	bootph-pre-ram;
};

&pinctrl_usdhc2_gpio {
	bootph-pre-ram;
};

&pinctrl_usdhc2 {
	bootph-pre-ram;
};

&pinctrl_usdhc3 {
	bootph-pre-ram;
};

&gpio1 {
	bootph-pre-ram;
};

&gpio2 {
	bootph-pre-ram;
};

&gpio3 {
	bootph-pre-ram;
};

&gpio4 {
	bootph-pre-ram;
};

&gpio5 {
	bootph-pre-ram;
};

&uart2 {
	bootph-pre-ram;
};

&usbmisc1 {
	bootph-pre-ram;
};

&usbphynop1 {
	bootph-pre-ram;
};

&usbotg1 {
	bootph-pre-ram;
};

&usdhc1 {
	bootph-pre-ram;
};

&usdhc2 {
	bootph-pre-ram;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	fsl,signal-voltage-switch-extra-delay-ms = <8>;
};

&usdhc3 {
	bootph-pre-ram;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
};

&i2c1 {
	bootph-pre-ram;
};

&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
	bootph-pre-ram;
};

&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
	bootph-pre-ram;
};

&pinctrl_i2c1 {
	bootph-pre-ram;
};

&pinctrl_pmic {
	bootph-pre-ram;
};

&pinctrl_wdog {
	bootph-pre-ram;
};

&fec1 {
	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};

&wdog1 {
	bootph-pre-ram;
};