tree 6f46d4b8d5e9cad5f969665f707d0b7374ef9130
parent f39f8f77a5268530e982aa38e921c640d532a9ae
author Torsten Duwe <duwe@lst.de> 1692029133 +0200
committer Leo Yu-Chi Liang <ycliang@andestech.com> 1693882416 +0800

riscv: jh7110: enable riscv,timer in the device tree

The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>