// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2019 NXP
// Author: Fabio Estevam <fabio.estevam@nxp.com>

/dts-v1/;

#include "imx7ulp.dtsi"
#include "imx7ulp-com-u-boot.dtsi"

/ {
	model = "Embedded Artists i.MX7ULP COM";
	compatible = "ea,imx7ulp-com", "fsl,imx7ulp";

	chosen {
		stdout-path = &lpuart4;
	};

	memory {
		device_type = "memory";
		reg = <0x60000000 0x8000000>;
	};
};

&lpuart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart4>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1_id>;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

&usbphy1 {
	fsl,tx-d-cal = <88>;
};

&usdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc0>;
	non-removable;
	bus-width = <8>;
	no-1-8-v;
	status = "okay";
};

&iomuxc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;

	pinctrl_hog_1: hoggrp-1 {
		fsl,pins = <
			IMX7ULP_PAD_PTC1__PTC1		0x20000
		>;
	};

	pinctrl_lpuart4: lpuart4grp {
		fsl,pins = <
			IMX7ULP_PAD_PTC3__LPUART4_RX	0x3
			IMX7ULP_PAD_PTC2__LPUART4_TX	0x3
		>;
	};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			IMX7ULP_PAD_PTD1__SDHC0_CMD	0x43
			IMX7ULP_PAD_PTD2__SDHC0_CLK	0x10042
			IMX7ULP_PAD_PTD3__SDHC0_D7	0x43
			IMX7ULP_PAD_PTD4__SDHC0_D6	0x43
			IMX7ULP_PAD_PTD5__SDHC0_D5	0x43
			IMX7ULP_PAD_PTD6__SDHC0_D4	0x43
			IMX7ULP_PAD_PTD7__SDHC0_D3	0x43
			IMX7ULP_PAD_PTD8__SDHC0_D2	0x43
			IMX7ULP_PAD_PTD9__SDHC0_D1	0x43
			IMX7ULP_PAD_PTD10__SDHC0_D0	0x43
			IMX7ULP_PAD_PTD11__SDHC0_DQS	0x42
		>;
	};

	pinctrl_usbotg1_id: otg1idgrp {
		fsl,pins = <
			IMX7ULP_PAD_PTC13__USB0_ID	0x10003
		>;
	};
};