tree 84d1764a5c706e3618b10b999781eab6e3b02142
parent 7e4db27ffd11f3eea7e4dfc33354fd087f9257d8
author York Sun <yorksun@freescale.com> 1345191762 +0000
committer Andy Fleming <afleming@freescale.com> 1345742216 -0500

powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only

Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>