tree 6a9e59f3b1672adb4266a19a8520cede20921cbb
parent 4b151562bb8e54160adedbc6a1c0c749c00a2f84
author Zong Li <zong.li@sifive.com> 1702562976 +0000
committer Leo Yu-Chi Liang <ycliang@andestech.com> 1703669337 +0800

cache: add sifive private L2 cache driver

This driver is currently responsible for enabling the clock gating
feature of SiFive pre core's private L2 cache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>