tree b9c64d1b3e2957b0522ed1ba5fbaa6a8f2cf1e3e
parent d67b98ed4790a30da9bdd337cfb76b03aac993e3
author Baruch Siach <baruch@tkos.co.il> 1579522807 +0200
committer Stefan Roese <sr@denx.de> 1579591909 +0100

arm: mvebu: clearfog: enable both DDR clocks

Enabled both DDR clock signals to support Clearfog variants (currently,
Clearfog GTR) that need both clocks.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>