tree 94d43c8ebe4c4905f1050516ac38ac5f2e9d5577
parent 811dd44b0b13cb1ea40392edfbe8ffa21c5b33ad
author Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 1699287719 +0100
committer Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 1710360940 +0100

mips: fix change_k0_cca()

The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.

Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.

Reported by user ddqxy138 on Github.
https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813cf4619

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>