tree 826c653c4a9efe0076dca4f88fc5217ad8413afc
parent b6f7ee5d1f980ffa63e22749e2deae6caa57227e
author Ley Foon Tan <ley.foon.tan@intel.com> 1553189041 +0800
committer Marek Vasut <marex@denx.de> 1555532417 +0200

ddr: altera: Stratix10: Add multi-banks DRAM size check

Stratix 10 maps dram from 0 to 128GB.  There is a 2GB hole
in the memory for peripherals and other IO from 2GB to 4GB.
However the dram controller ignores upper address bits for
smaller dram configurations.  Example: a 4GB dram
maps to multiple locations, every 4GB on the address.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>