tree c34f38c831d61a5f2943ff96658f1f98e764061f
parent b2486b40dce98ca26bcb6e1dda69efb1b0443b9a
author Joakim Tjernlund <joakim.tjernlund@infinera.com> 1505239001 +0200
committer York Sun <york.sun@nxp.com> 1533741828 -0700

FSL PCI: Configure PCIe reference ratio

Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.

This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>