tree 318d2f24a27faf9100ec8968c7adef3472b44563
parent 5cf049c00ac0c5c9542ce968d9f79451ce870b2c
author Shivamurthy Shastri <sshivamurthy@micron.com> 1594152251 +0200
committer Jagan Teki <jagan@amarulasolutions.com> 1595264313 +0530

mtd: spinand: micron: identify SPI NAND device with Continuous Read mode

Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>