tree 257ddcaf4039dd6722e743e8a1f4035c2f85387f
parent 3e8650c0f9cc7fb29bd75c11d0173768fcc80203
author Tom Warren <twarren@nvidia.com> 1435251044 -0700
committer Tom Warren <twarren@nvidia.com> 1438813371 -0700

Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.

Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.

Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>