tree 85eb9638e349fc764f0733458df6d56a123edfb0
parent 0778bbe2d42dade68350d14a6314cfff1f4ba939
author Valentin Longchamp <valentin.longchamp@keymile.com> 1382089640 +0200
committer York Sun <yorksun@freescale.com> 1382632552 -0700

mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it

If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.

This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
RAM chips (no module used, chips directly soldered on board with an SPD
EEPROM).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix minor conflicts in fsl_ddr_dimm_params.h,
	   lc_common_dimm_params.c, common_timing_params.h]
Acked-by: York Sun <yorksun@freescale.com>