tree 5be0c5e2b0b2fd18c67f6fbc52acfd04464f4a65
parent 480a9b834c661fc88217f50bdf780192c3018d66
author Xu Ziyuan <xzy.xu@rock-chips.com> 1492335883 +0800
committer Simon Glass <sjg@chromium.org> 1494445041 -0600

rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>