tree fa1cf8a170572b65af737680b1000d0324099c60
parent e5852787f0c3c442a276262f13d91ca450605ac0
author Kumar Gala <galak@kernel.crashing.org> 1216062422 -0500
committer Andrew Fleming-AFLEMING <afleming@freescale.com> 1216084799 -0500

85xx: Add some L1/L2 SPR register definitions

Add new L1/L2 SPRs related to e500mc cache config and control.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>