tree c2110ae5869ee47a86d19f73bade247db5d94b13
parent c8dd0e42d709c9734f313c547d0707e27ca0de51
author Heiko Stuebner <heiko.stuebner@theobroma-systems.com> 1574161442 +0100
committer Kever Yang <kever.yang@rock-chips.com> 1574523704 +0800

rockchip: px30: enable spl-fifo-mode for both emmc and sdmmc on evb

As part of loading trustedfirmware, the SPL is required to place portions
of code into the socs sram but the mmc controllers can only do dma
transfers into the regular memory, not sram.

The results of this are not directly visible in u-boot itself, but
manifest as security-relate cpu aborts during boot of for example Linux.

There were a number of attempts to solve this elegantly but so far
discussion is still ongoing, so to make the board at least boot correctly
put both mmc controllers into fifo-mode, which also circumvents the
issue for now.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>