tree 499ccc1cbbb52182227112a9fb7eb37fc7bfafe9
parent aa8ac43645243b69faf0e81fab5f0d6fcf4285cf
author Lokesh Vutla <lokeshvutla@ti.com> 1424061956 +0530
committer Tom Rini <trini@ti.com> 1424108500 -0500

ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>