tree 272a979e6e9ed0ae0ab583068657c33793b4355c
parent aca5f018a8386b85469482ed9867e3e29a2437d0
author Dave Liu <daveliu@freescale.com> 1227256282 +0800
committer Andrew Fleming-AFLEMING <afleming@freescale.com> 1232751793 -0600

fsl-ddr: update the bit mask for DDR3 controller

According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.

Signed-off-by: Dave Liu <daveliu@freescale.com>