// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)
 *
 * (C) Copyright 2019 - 2022, Xilinx, Inc.
 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

/dts-v1/;
/plugin/;

/{
	compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03";

	fragment@0 {
		target = <&dc_i2c>;

		__overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;

			x_prc_eeprom: eeprom@52 { /* u1 */
				compatible = "atmel,24c02";
				reg = <0x52>;
			};

			x_prc_tca9534: gpio@22 { /* u3 tca9534 */
				compatible = "nxp,pca9534";
				reg = <0x22>;
				gpio-controller; /* IRQ not connected */
				#gpio-cells = <2>;
				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
						  "", "", "", "";
				gtr-sel0-hog {
					gpio-hog;
					gpios = <0 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_1";
				};
				gtr-sel1-hog {
					gpio-hog;
					gpios = <1 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_2";
				};
				gtr-sel2-hog {
					gpio-hog;
					gpios = <2 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_3";
				};
				gtr-sel3-hog {
					gpio-hog;
					gpios = <3 0>;
					input; /* FIXME add meaning */
					line-name = "sw4_4";
				};
			};
			x_prc_si5338: clock-generator@70 { /* U9 */
				compatible = "silabs,si5338";
				reg = <0x70>; /* FIXME */
			};
		};
	};

	fragment@1 {
		target = <&i2c1>; /* Must be enabled via J90/J91 */
		__overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;

			eeprom_versal: eeprom@51 { /* u2 */
				compatible = "atmel,24c02";
				reg = <0x51>;
			};
		};
	};
};