tree ae45e6bcfb09551775df7068f8d94a9406ac087a
parent bba7711092a48ef2af00832213c3cb6c2d5f171c
author Marek Vasut <marex@denx.de> 1459783696 +0200
committer Marek Vasut <marex@denx.de> 1461144524 +0200

ddr: altera: Fix scc_mgr_set() argument order

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>