tree 6aa03fa40583e3abbfc9a0accfca1b5c4a016b0a
parent 9d43649a7740cf715c750929d19661a35144e7d1
author Masahiro Yamada <yamada.masahiro@socionext.com> 1545217400 +0900
committer Masahiro Yamada <yamada.masahiro@socionext.com> 1546051118 +0900

clk: uniphier: add NAND 200MHz clock

The Denali NAND controller IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

Currently, only the first one (50MHz) is provided.  The rest of the
two clock ports must be connected to the 200MHz clock line.  Add this.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>