tree 3af577ebb7be24efd3c23d7a8559512d2f9bfa70
parent eb5394120643922626f18e5fe7b0b3dc0ed43b9a
author York Sun <yorksun@freescale.com> 1349682266 +0000
committer Andy Fleming <afleming@freescale.com> 1350934289 -0500

powerpc/mpc85xx: Add workaround for DDR erratum A004934

After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>